參數(shù)資料
型號： SPC5634MF1MMG80
廠商： Freescale Semiconductor
文件頁數(shù)： 73/122頁
文件大?。?/td> 0K
描述： IC MCU FLASH 1.5M 94K 208-PBGA
標準包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z3
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，EBI/EMI，LIN，SCI，SPI，UART/USART
外圍設備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 114
程序存儲器容量： 1.5MB（1.5M x 8）
程序存儲器類型： 閃存
RAM 容量： 94K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.25 V
數(shù)據(jù)轉換器： A/D 34x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 150°C
封裝/外殼： 208-BGA
包裝： 托盤
MPC5634M Microcontroller Data Sheet, Rev. 9
Pinout and signal description
Freescale Semiconductor
54
Table 5 gives the power/ground segmentation of the MPC563x MCU. Each segment provides the power and ground for the
given set of I/O pins, and can be powered by any of the allowed voltages regardless of the power on the other segments.
.
NMI
SIU – External
Interrupts
Non-Maskable Interrupt
GPIO[n]
SIU – GPIO
Configurable general purpose I/O pins. Each GPIO input and
output is separately controlled by an 8-bit input (GPDI) or output
(GPDO) register. Additionally, each GPIO pins is configured
using a dedicated SIU_PCR register.
The GPIO pins are generally multiplexed with other I/O pin
functions.
RESET
SIU – Reset
The RESET pin is an active low input. The RESET pin is
asserted by an external device during a power-on or external
reset. The internal reset signal asserts only if the RESET pin
asserts for 10 clock cycles. Assertion of the RESET pin while the
device is in reset causes the reset cycle to start over.
The RESET pin has a glitch detector which detects spikes
greater than two clock cycles in duration that fall below the
switch point of the input buffer logic of the VDDEH input pins.
The switch point lies between the maximum VIL and minimum
VIH specifications for the VDDEH input pins.
RSTOUT
SIU – Reset
The RSTOUT pin is an active low output that uses a push/pull
configuration. The RSTOUT pin is driven to the low state by the
MCU for all internal and external reset sources. There is a delay
between initiation of the reset and the assertion of the RSTOUT
pin.
Table 5. MPC563x Power/Ground Segmentation
Power
Segment
144-LQFP
Pin
Number
176-LQFP
Pin
Number
208-BGA
Pin
Number
Voltage
Range1
I/O Pins Powered
by Segment
VDDA0
6
B11
5.0 V
AN[0:7], AN[9], AN[11],
AN[16:18], AN[21:25],
AN[27:28], AN[30:37],
AN38, AN39, VRL,
REFBYPC,
VRH
VDDE5
—
T13
1.8 V –
3.3 V
CLKOUT
VDDEH1
(a,b)
24, 34
31, 41
K4
3.3 V –
5.0 V
PCKCFG[2],
eTPU_A[0:31],
eMIOS[0:2]
Table 4. Signal details (continued)
Signal
Module or Function
Description
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