參數資料
型號： SPC5634MF1MMG80
廠商： Freescale Semiconductor
文件頁數： 37/122頁
文件大?。?/td> 0K
描述： IC MCU FLASH 1.5M 94K 208-PBGA
標準包裝： 90
系列： MPC56xx Qorivva
核心處理器： e200z3
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，EBI/EMI，LIN，SCI，SPI，UART/USART
外圍設備： DMA，POR，PWM，WDT
輸入/輸出數： 114
程序存儲器容量： 1.5MB（1.5M x 8）
程序存儲器類型： 閃存
RAM 容量： 94K x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.25 V
數據轉換器： A/D 34x12b
振蕩器型： 內部
工作溫度： -40°C ~ 150°C
封裝/外殼： 208-BGA
包裝： 托盤
Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
21
– SCK to PCS delay
– Delay between frames
— Programmable serial frame size of 4 to 16 bits, expandable with software control
— Continuously held chip select capability
6 Peripheral Chip Selects, expandable to 64 with external demultiplexer
Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer
DMA support for adding entries to TX FIFO and removing entries from RX FIFO:
— TX FIFO is not full (TFFF)
— RX FIFO is not empty (RFDF)
6 Interrupt conditions:
— End of queue reached (EOQF)
— TX FIFO is not full (TFFF)
— Transfer of current frame complete (TCF)
— Attempt to transmit with an empty Transmit FIFO (TFUF)
— RX FIFO is not empty (RFDF)
— FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty)
— FIFO Overrun (serial frame received while RX FIFO is full)
Modified transfer formats for communication with slower peripheral devices
Continuous Serial Communications Clock (SCK)
Power savings via support for Stop Mode
Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the Microsecond
Channel downstream frame format
The DSPIs also support these features unique to the DSI and CSI configurations:
2 sources of the serialized data:
— eTPU_A and eMIOS output channels
— Memory-mapped register in the DSPI
Destinations for the deserialized data:
— eTPU_A and eMIOS input channels
— SIU External Interrupt Request inputs
— Memory-mapped register in the DSPI
Deserialized data is provided as Parallel Output signals and as bits in a memory-mapped register
Transfer initiation conditions:
— Continuous
— Edge sensitive hardware trigger
— Change in data
Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
Continuous serial communications clock
Support for parallel and serial chaining of up to four DSPI blocks
2.2.16
eSCI
The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and
other MCUs. It includes special support to interface to Local Interconnect Network (LIN) slave devices. The eSCI block
provides the following features:
Full-duplex operation
Standard mark/space non-return-to-zero (NRZ) format
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