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參數(shù)資料
| 型號(hào)： | SPC5634MF1MMG80 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 39/122頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 208-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心處理器： | e200z3 |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 114 |
| 程序存儲(chǔ)器容量： | 1.5MB（1.5M x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 94K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 34x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 208-BGA |
| 包裝： | 托盤(pán) |
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Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
23
Selectable backwards compatibility with previous FlexCAN versions
Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock
Listen only mode capability
Programmable loop-back mode supporting self-test operation
3 programmable Mask Registers
Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority
Time Stamp based on 16-bit free-running timer
Global network time, synchronized by a specific message
Maskable interrupts
Warning interrupts when the Rx and Tx Error Counters reach 96
Independent of the transmission medium (an external transceiver is assumed)
Multi master concept
High immunity to EMI
Short latency time due to an arbitration scheme for high-priority messages
Low power mode, with programmable wake-up on bus activity
2.2.18
System timers
The system timers provide two distinct types of system timer:
Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)
Operating system task monitors using the System Timer Module (STM)
2.2.18.1
Periodic Interrupt Timer (PIT)
The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has
no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as
periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by
the crystal clock. This one channel is also referred to as Real Time Interrupt (RTI) and is used to wakeup the device from low
power stop mode.
The following features are implemented in the PIT:
5 independent timer channels
Each channel includes 32-bit wide down counter with automatic reload
4 channels clocked from system clock
1 channel clocked from crystal clock (wake-up timer)
Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined
timeout period
Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer
reaches zero
2.2.18.2
System Timer Module (STM)
http://www.autosar.org). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer
comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.
The following features are implemented in the STM:
One 32-bit up counter with 8-bit prescaler
Four 32-bit compare channels
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