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參數(shù)資料
| 型號(hào)： | SPC5634MF1MMG80 |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 30/122頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH 1.5M 94K 208-PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | MPC56xx Qorivva |
| 核心處理器： | e200z3 |
| 芯體尺寸： | 32-位 |
| 速度： | 80MHz |
| 連通性： | CAN，EBI/EMI，LIN，SCI，SPI，UART/USART |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 114 |
| 程序存儲(chǔ)器容量： | 1.5MB（1.5M x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 94K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 34x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 150°C |
| 封裝/外殼： | 208-BGA |
| 包裝： | 托盤(pán) |
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Overview
MPC5634M Microcontroller Data Sheet, Rev. 9
Freescale Semiconductor
15
The flash memory provides the following features:
Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword
reads are supported. Only aligned word and doubleword writes are supported.
Fetch Accelerator
— Architected to optimize the performance of the flash with the CPU to provide single cycle random access to the
flash up to 80 MHz system clock speed
— Configurable read buffering and line prefetch support
— Four line read buffers (128 bits wide) and a prefetch controller
Hardware and software configurable read and write access protections on a per-master basis
Interface to the flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in
parallel for interleaved or pipelined flash array designs
Configurable access timing allowing use in a wide range of system frequencies
Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation
of other memory types
Software programmable block program/erase restriction control
Erase of selected block(s)
Read page size of 128 bits (four words)
ECC with single-bit correction, double-bit detection
Program page size of 64 bits (two words)
ECC single-bit error corrections are visible to software
Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC
Embedded hardware program and erase algorithm
Erase suspend
Shadow information stored in non-volatile shadow block
Independent program/erase of the shadow block
2.2.10
SRAM
The MPC5634M SRAM module provides a general-purpose up to 94 KB memory block. The SRAM controller includes these
features:
Supports read/write accesses mapped to the SRAM memory from any master
32 KB or 24 KB block powered by separate supply for standby operation
Byte, halfword, word and doubleword addressable
ECC performs single-bit correction, double-bit detection on 32-bit data element
2.2.11
BAM
The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by Freescale and is identical for all
MPC5634M MCUs. The BAM program is executed every time the MCU is powered-on or reset in normal mode. The BAM
supports different modes of booting. They are:
Booting from internal flash memory
Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)
Booting from external memory on calibration bus
The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the MPC5634M
hardware accordingly. The BAM provides the following features:
Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address
translation
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