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參數(shù)資料
| 型號(hào)： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁數(shù)： | 28/117頁 |
| 文件大?。?/td> | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
4.2 SERIAL COMMUNICATIONSINTERFACE
4.2.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of Baud rates thanks to the
presence of two Baud rate generator systems: the
first is of conventional type and yields common
communications Baud rates with standard oscilla-
tor frequencies; the second features a program-
mable prescaler capable of dividing the input fre-
quency by any factor from 1 to 255, thus offering a
very wide range of Baud rates even with non-
standard oscillator frequencies. Transmitter and
Receiver circuits are independent and can operate
at different Baud rates; indeed, each can select ei-
ther type of Baud rate generator. External connec-
tions are by means of two I/O pins: TDO (Port
PB0) for the Transmit Data output and RDI (Port
PB1) for the Receive Data input.
4.2.2 Features
– Full duplex, asynchronous communications
– NRZ standard format (Mark/Space)
– Dual Baud rate generator systems
– Independently programmable transmission and
reception Baud rates
– Separate Transmit and Receive Baud rates
– Programmable word length (8 or 9 bits)
– Receive buffer full, Transmit buffer empty and
End of Transmission flags
– Receiver wake-up function by the most signifi-
cant bit or by idle line
– Muting function for multiprocessor configurations
– Separate enable bitsforTransmitter andReceiver
– Noise, Overrun and Frame Error detection
– Four interrupt sources with flags
– Overall accuracy better than 1% of Baud rate.
4.2.3 Serial Data Format
Serial data is transmitted and received as frames
comprising the following elements:
– An Idle Line in the ”high” state prior to transmis-
sion or reception.
– A Start bit in the ”low” state, denoting the start of
each character.
– Character dataword (8or 9 bits), least significant
bit first.
– A Stop bit in the ”high” state, indicating that the
frame is complete.
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCCR1 con-
trol register.
An Idle Line condition is interpreted on receiving
an entire frame of ”ones”.
A Break is interpreted on receiving ”zeros” for
some multiple of the frame period.
4.2.4 Data Reception and Transmission
The following description is best read with refer-
ence to the SCI Block Diagram illustrated in Figure
1, where it will be noted that the SCDR data regis-
ter is shown as two separate registers, one for
transmitted data and the other for received data.
The Serial Communications DataRegister (SCDR)
performs a dual function (Read And Write), since it
accesses two separate registers, one for transmis-
sion (TDR) and one for reception (RDR). The TDR
register provides thedata interface between the in-
ternal bus and theoutput shiftregister for data to be
transmitted, while the RDR register provides an in-
terface between the input shift register and the in-
ternal bus for incoming data.
When the SCDR is read, the RDR is accessed and
its contents are transferred to the data bus. The
RDRF (RDR Full Flag) in the SCSR register is set
to ”1” as soon as the word in the receiver shift reg-
ister is transferred to the RDR register.
When the SCDR is written to, the data word is
transferred to the TDR register. The TDRE flag
(TDR empty) in the SCSR register is set to ”1” as
soon as the word in the TDR is transferred to the
transmit shift register.
Incoming data is received in a serial shift register
and then transferred to a parallel Receive Data
Register (RDR) as a complete word, thus allowing
the next incoming character to be received in the
shift register while the current character is still in
the RDR.
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
4.2.5 Receiver Muting and Wake-up Feature
In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overheads
for all non addressed receivers. Communications
protocols in such configurations generally issue
the recipient address as a message header.
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