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參數(shù)資料
| 型號(hào)： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤(pán)，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 45/117頁(yè) |
| 文件大小： | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
4.4 SERIAL PERIPHERAL INTERFACE
4.4.1 Introduction
The Serial Peripheral Interface (SPI) allows devic-
es to be interconnected using a minimum of wires.
The SPI is synchronous and thus uses a data and
a clock signal; in complex arrays, chip select lines
may also be used. An SPI system may be config-
ured as a Master and one or more Slaves, or as a
system in which devices may be either Masters or
Slaves. Depending on MCU specifications, one or
more SPIs may be present.
4.4.2 Features
– Full duplex, three-wire synchronous transfers
– Master or Slave operation
– 2 MHz (maximum) Master bit frequency
– 4 MHz (maximum) Slave bit frequency
– Four programmable Master bit rates
– Programmable clock polarity and phase
– End of transmission interrupt flag
– Write collision flag protection
– Master mode fault protection capability.
4.4.3 Functional Description
A block diagram of the Serial Peripheral Interface
(SPI) is shown inFigure 27. In a Master configura-
tion, the Master start logic receives an input from
the CPU (in the form of a write to the SPI rate gen-
erator data register) and originates the system
clock (SCK) based on the internal processor
clock. This clock is also used internally to control
the state controller as well as the 8-bit shift regis-
ter.
As a Master device, data is parallel loaded into the
8-bit shift register (from the internal bus) during a
write cycle, and then shifted out serially via the
MOSI pin to the Slave device(s). During a read cy-
cle, data is received serially from a Slave device
via the MISO pin and loaded into to the 8-bit shift
register. When the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer and
then made available to the internal data bus during
a CPU read cycle.
In Slave configuration, the Slave start logic re-
ceives a logic low level (from a Master device) on
the SS pin, and a system clock input (from the
same Master device) on the SCK pin. Thus, the
Slave is synchronized with the Master. Data from
the Master is received serially on the Slave MOSI
pin and is loaded into the 8-bit shift register.
Once the 8-bit shift register is loaded, its data is
parallel transferred to the read buffer and then is
made available to the internal data bus during a
CPU read cycle. During a write cycle, data is par-
allel loaded into the 8-bit shift register from the in-
ternal data bus and then shifted out serially to the
MISO pin for application to the Master device.
Figure 29 illustrates the MOSI, MISO and SCK
Master-Slave interconnections. Note that the Mas-
ter SS pin is tied to a logic high level and the Slave
SS pin to a logic low level.
Three registers are associated with each SPI inter-
face:
the
Serial
Peripheral
(SPCR), the Serial Peripheral Status Register
(SPSR), and the Serial Peripheral Data I/O regis-
ter (SPDR). These provide Control, Status, and
Data functions. These registers are described in
detail in the following pages.
Control
Register
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