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參數(shù)資料
| 型號(hào)： | ST72T85A5Q6 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES |
| 中文描述： | 8位微控制器48,000鐵路發(fā)展策略光盤(pán)，3K內(nèi)存，ADC，兩個(gè)定時(shí)器，2個(gè)SPI，I2C和脊髓損傷接口 |
| 文件頁(yè)數(shù)： | 61/117頁(yè) |
| 文件大?。?/td> | 748K |
| 代理商： | ST72T85A5Q6 |
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ST7285C
I
2
C BUS INTERFACE
(Cont’d)
STATUS REGISTER 2 (SR2)
Address: 002Ah
Reset Value: 00h
—
Read Only
b7-5 = reserved.
b4:
AF
Acknowledge Failure
The Acknowledge Failure bit is set when no ac-
knowledge is returned. If this bit is set, then an in-
terrupt is sent to the microcontroller if ITE is set.
During this interrupt, the SCL line is not hold low.
This bit is cleared by a read of the Status Register.
It is also cleared when the peripheral is disabled
(PE=0) or by reset.
b3:
STOPF
Stop Detection Flag (in Slave mode)
StopF bit is set when a Stop condition is detected
on the SCL line after an acknowledge of byte.
When this bit is set, an interrupt is sent to the mi-
crocontroller if ITE is set. During this interrupt, the
SCL line is not hold low.
This bit is cleared by a read of the status register
(when StopF is set). Itis also cleared when the pe-
ripheral is disabled (PE=0) or by reset.
b2:
ARLO
Arbitration Lost
ARLO is set when the I
2
C interface loses the arbi-
tration of the bus to another Master. After ARLO is
set, the interface operates in Slave mode (M/SL at
a logic low) and an interrupt is generated if ITE is
set. During this interrupt, the SCL line is not hold
low.
This bit is cleared by a read of the Status register.
It is also cleared when the peripheral is disabled
(PE=0) or by reset.
b1:
BERR
Bus Error
BERR bit is set when a misplaced start or stop
condition is detected. If this bit is set, then an inter-
rupt is sent to the microcontroller if ITE is set. Dur-
ing this interrupt, the SCL line is not hold low.
The Bus Error flag bit is cleared by a read of the
status register (when BERR is set). It is also
cleared when the peripheral is disabled (PE=0) or
by reset.
b0:
GCAL
General Call (Slave mode)
If ENGC is set, GCAL is set following detection of
a general call address.
It is cleared by the detection of a stop condition, by
reset or when the peripheral is disabled (PE=0).
4.5.6 I
2
C State Machine:
In I
2
C mode, the I
2
C interface always operates in
Slave mode (M/SL at logic low level) except when
it initiates a transmission or a receive sequence.
It enables the multimaster function with an auto-
matic switch from Master mode to Slave mode
when the interface loses the arbitration of the I
2
C
bus. So, the Slave process is active both in Slave
mode and in Master mode.
4.5.6.1 Slave mode
As soon as a start condition is detected, the ad-
dress word is received from the SDA line and it is
sent to the shift register; then it is compared with
the interface address.
– Address no matched: the state machine is reset
and it waits for another Start bit.
– Address matched: the Addressed As Slave bit
(ADSL) is set and an acknowledge bit is sent to
the Master if ACK is set. So an interrupt is sentto
the microcontroller if ITE is set; it then waits for
the microcontroller to read Status Register 1 by
holding the SCL line low.
Then, depending on the Data Direction bit (least
significant bit), and after generating an acknowl-
edge, the Slave must enter Send or Receive
mode.
4.5.6.2 Slave Receiving
The Slave receives words from the SDA line into
the shift register and it sends them to the data reg-
ister. After each word it generates an acknowledge
bit if the Enable Acknowledge flag is set. When the
acknowledge bit is sent, the BTF flag is set and an
interrupt is generated if ITE is set.Then it waits for
the microcontroller to read the Data Register by
holding the SCL line low.
- Detection of a Stop or a Start condition during a
byte reception: the BERR flag is set and an inter-
rupt is generated.
- Detection of a Start condition after an acknowl-
edge time-slot: the state machine is reset and
starts a new process.
- Detection of a Stop condition after an acknowl-
edge time-slot: the Slave state machine is reset.
Then the SSTOP flag is set and an interrupt is
generated if ITE is set.
- The Stop bit is set in the control register: the state
machine is reset after transfer of the current byte.
7
0
-
-
-
AF
STOPF
ARLO
BERR
GCAL
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