參數(shù)資料
型號： ST72T85A5Q6
廠商： 意法半導(dǎo)體
英文描述： 8-BIT MCU FOR RDS WITH 48K ROM, 3K RAM, ADC, TWO TIMERS, TWO SPIs, I2C AND SCI INTERFACES
中文描述： 8位微控制器48,000鐵路發(fā)展策略光盤，3K內(nèi)存，ADC，兩個定時器，2個SPI，I2C和脊髓損傷接口
文件頁數(shù)： 75/117頁
文件大?。?/td> 748K
代理商： ST72T85A5Q6
75/117
ST7285C
RDS G.B.S.
(Cont’d)
4.9.3.3 GBS Registers
Sixteen registers are dedicated to interfacing the
Group and Block Synchronization module to the
CPU.
These registers, together with their symbolic
names, bit names and address are presented in
tabular form in Table 10 below and are here de-
scribed in greater detail.
Register Reset States: all registers bits are set to
“0” during Reset, except for CNA4-CNA0, CNB1,
CNB0 and ORD, which are set to “1”.
SRx - Shift Registers
b7,6 =
SR0:
contain the 2 last transmitted bits
c1’,c0’ of the checkword.
b5-0 are not used and are always read as “0”.
b7-0 =
SR1:
contain the 8 first transmitted bits
(c9’...c2’) of the checkword.
b7-0 =
SR2:
contain the 8 last information bits
(m7’...m0’) of the message vector.
b7-0 =
SR3:
contain the 8 first information bits
(m15’...m8’) of the message vector.
SY0 - Polynomial Register 0
b7,6 =
SY0:
contain the 2 least significant bits of
the calculated syndrome. For valid syndromes,
these two bits are “0.
b5 is not used, and is always read as “0”.
b4 =
US
(USA option). Setting US to “1” enables
detection of block E.
b3 =
ORD
flag. Set to “1” when block counter
CB[1:0] is equal to block code BL[1:0]: otherwise it
is “0”. Stable with VSI or CNI. Read only. Reset
Value is one.
b2-0 =
BL[2:0]
block code, see Table 9. Stable
with CNI or VSI. Read only.
SY1 - Polynomial Register 1
b7-0 =
SY1:
contain the 8 most significant bits
(p9’...p2’) of the calculated syndrome.
Table 10. GBS Register Map
Register
Address
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SR0 - shift reg. 0
0060h
c
1
’
c
0
’
-
-
-
-
-
-
SR1 - shift reg. 1
0061h
c
9
’
c
8
’
c
7
’
c
6
’
c
5
’
c
4
’
c
3
’
c
2
’
SR2 - shift reg. 2
0062h
m
7
m
6
m
5
m
4
m
3
m
2
m
1
m
0
SR3 - shift reg. 3
0063h
m
15
m
14
m
13
m
12
m
11
m
10
m
9
m
8
SY0 - polynomial reg. 0
0064h
p
1
p
0
-
US
ORD
BL2
BL1
BL0
SY1 - polynomial reg. 1
0065h
p
9
p
8
p
7
p
6
p
5
p
4
p
3
p
2
GS_CNT - count reg.
0066h
CNB1
CNB0
SYNC
CNA4
CNA3
CNA2
CNA1
CNA0
GS_INT - interrupt reg.
0067h
CAL
CAR
ECM
VSI
VSE
CNI
CE1
CE0
DR0 - RDSDAT reg. 0
0068h
DR1
DR0
-
MQE
SQE
QAL
RCL
RDA
DR1 - RDSDAT reg. 1
0069h
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR2 - RDSDAT reg. 2
006Ah
DR17
DR16
DR15
DR14
DR13
DR12
DR11
DR10
DR3 - RDSDAT reg. 3
006Bh
DR25
DR24
DR23
DR22
DR21
DR20
DR19
DR18
QR0 - QUALITY reg. 0
006Ch
QR1
QR0
-
-
-
-
-
-
QR1 - QUALITY reg. 1
006Dh
QR9
QR8
QR7
QR6
QR5
QR4
QR3
QR2
QR2 - QUALITY reg. 2
006Eh
QR17
QR16
QR15
QR14
QR13
QR12
QR11
QR10
QR3 - QUALITY reg. 3
006Fh
QR25
QR24
QR23
QR22
QR21
QR20
QR19
QR18
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