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參數(shù)資料
| 型號： | TFRA08C13 |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 59/188頁 |
| 文件大小： | 3047K |
| 代理商： | TFRA08C13 |
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Lucent Technologies Inc.
59
Preliminary Data Sheet
October 2000
TFRA08C13 OCTAL T1/E1 Framer
CEPT Time Slot 0 FAS/NOT FAS Control Bits
(continued)
NOT FAS Sa Stack Source and Destination
The transmit Sa4 to Sa8 bits may be sourced from the transmit Sa stack, registers FRM_PR31—FRM_PR40. The
Sa stack consists of ten 8-bit registers that contain 16 NOT FAS frames of Sa information as shown in Table 22.
The transmit stack data may be transmitted either in non-CRC-4 mode or in CRC-4 mode to the line.
The receive stack data, registers FRM_SR54—FRM_SR63, is valid in both the non-CRC-4 mode and the CRC-4
mode. In the non-CRC-4 mode while in the loss of frame alignment (LFA) state, updating of the receive Sa stack is
halted and the transmit and receive stack interrupts are deactivated. In the CRC-4 mode while in the loss of time
slot 0 multiframe alignment (LTS0MFA) state, updating of the receive Sa stack is halted and the transmit and
receive stack interrupts are deactivated.
Table 22. Transmit and Receive Sa Stack Structure
The most significant bit of the first byte is transmitted to the line in frame 1 of a double CRC-4 multiframe. The least
significant bit of the second byte is transmitted to the line in frame 31 of the double CRC-4 multiframe. The protocol
for accessing the Sa Stack information for the transmit and receive Sa4 to Sa8 bits is shown in Figure 16 and
described briefly below.
The device indicates that it is ready for an update of its transmit stack by setting register FRM_SR4 bit 7 (CEPT
transmit Sa stack ready) high. At this time, the system has about 4 ms to update the stack. Data written to the stack
during this interval will be transmitted during the next double CRC-4 multiframe. By reading register FRM_SR4
bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. If the transmit stack
is not updated, then the content of the stack is retransmitted to the line. The 32-frame interval of the transmit framer
in the non-CRC-4 mode is arbitrary. Enabling transmit CRC-4 mode forces the updating of the internal transmit
stack at the end of the 32-frame CRC-4 double multiframe; the transmit Sa stack is then transmitted synchronous
to the transmit CRC-4 multiframe structure.
On the receive side, the TFRA08C13 indicates that it has received data in the receive Sa stack, register
FRM_SR54—FRM_SR63, by setting register FRM_SR4 bit 6 (CEPT receive Sa stack ready) high. The system
then has about 4 ms to read the contents of the stack before it is updated again (old data lost). By reading register
FRM_SR4 bit 6, the system clears this bit so that it can indicate the next time the receive stack is ready. The
receive framer always updates the content of the receive stack so unread data will be overwritten. The last 16 valid
Sa4 to Sa8 bits are always stored in the receive Sa stack on a double-multiframe boundary. The 32-frame interval
of the receive framer in the non-CRC-4 mode is arbitrary. Enabling the receive CRC-4 mode forces updating of the
receive Sa stack at the end of the 32-frame CRC-4 double multiframe. The receive Sa stack is received synchro-
nous to the CRC-4 multiframe structure.
Register
Number
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
+
Bit 0
(LSB)
1
2
3
4
5
6
7
8
9
10
Sa4-1
Sa4-17
Sa5-1
Sa5-17
Sa6-1
Sa6-17
Sa7-1
Sa7-17
Sa8-1
Sa8-17
Sa4-3
Sa4-19
Sa5-3
Sa5-19
Sa6-3
Sa6-19
Sa7-3
Sa7-19
Sa8-3
Sa8-19
Sa4-5
Sa4-21
Sa5-5
Sa5-21
Sa6-5
Sa6-21
Sa7-5
Sa7-21
Sa8-5
Sa8-21
Sa4-7
Sa4-23
Sa5-7
Sa5-23
Sa6-7
Sa6-23
Sa7-7
Sa7-23
Sa8-7
Sa8-23
Sa4-9
Sa4-25
Sa5-9
Sa5-25
Sa6-9
Sa6-25
Sa7-9
Sa7-25
Sa8-9
Sa8-25
Sa4-11
Sa4-27
Sa5-11
Sa5-27
Sa6-11
Sa6-27
Sa7-11
Sa7-27
Sa8-11
Sa8-27
Sa4-13
Sa4-29
Sa5-13
Sa5-29
Sa6-13
Sa6-29
Sa7-13
Sa7-29
Sa8-13
Sa8-29
Sa4-15
Sa4-31
Sa5-15
Sa5-31
Sa6-15
Sa6-31
Sa7-15
Sa7-31
Sa8-15
Sa8-31
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相關(guān)代理商/技術(shù)參數(shù) |
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