參數(shù)資料
型號(hào)： THS8210PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 34/73頁(yè)
文件大?。?/td> 2053K
代理商： THS8210PFP
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
4
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
connected to this port. In 10-bit input mode this port is
unused. In 20-bit input mode this port is used for CbCr input
data.
31
DVSS
PWR
Digital core ground
32
DVDD
PWR
Digital core power, nominal 1.8V
33 to 42
RCr[9:0]
I
10-bit video data input port. All 10-bits or 8 MSB bits of this
port can be connected to the video data source. In 30-bit
mode, the R data of RGB, or the Cr data of YCbCr, should be
connected to this port. In 10- or 20-bit input modes, this port is
unused.
43
HS_IN
I or O
Horizontal source synchronization. In ‘slave timing mode’, this
is an input from the video data source. In ‘master timing
mode’, this is an output to the video data source with
programmable timing and polarity, in order to serve as a
horizontal data qualification signal to the video source.
44
VS_IN
I or O
Vertical source synchronization. In ‘slave timing mode’, this is
an input from the video data source. In ‘master timing mode’,
this is an output to the video data source with programmable
timing and polarity, in order to serve as a vertical data
qualification signal to the video source.
45
GND_IO
PWR
IO ring ground
46
VDD_IO
PWR
IO ring power, 1.8V or 3.3V nominal
47
FID
I or O
Field identification signal for interlaced video formats.
In ‘slave timing’ mode, this is an input from the video data
source. In ‘master timing mode’, this is an output to the video
data source with programmable timing and polarity, in order to
serve as a field qualification signal to the video source.
48 to 57
GY[9:0]
I
10-bit video data input port. All 10-bits or 8 MSB bits of this
port can be connected to the video data source. The G data
of RGB, or the Y data of YCbCr, should be connected to this
port. Port used in 10-bit mode for D1 video input data; in 20-
bit input mode for Y data.
58
DVSS
PWR
Digital core ground
59
DVDD
PWR
Digital core power, nominal value is 1.8V
60
RESETB
I
Software reset pin (active low). The minimum reset pulse
width is 200 ns.
61
HS_OUT
O
Horizontal
sync
output
(to
display).
Irrespective
of
‘slave/master timing mode’ configuration, this is always an
output with timing generated by the DTG.
62
VS_OUT
O
Vertical sync output (to display). Irrespective of ‘slave/master
timing mode’ configuration, this is always an output with
timing generated by the DTG.
63
SDA
B
Serial data line of I2C bus interface. Open-collector.
64
SCL
B
Serial clock line of I2C bus interface. Open-collector.
Maximum guaranteed clock speed is 400kHz (Fast I2C).
65 to 69
DO[9:5]
O
ITU-R BT656 compliant video data output port. Only available
when ITU-R.BT656 input format is used. Can be used to
connect to external PAL/NTSC video encoder. This port is
default off and should be activated via an I2C register setting.
70
VDD_IO
PWR
IO ring power, 1.8V or 3.3V nominal
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