參數(shù)資料
型號(hào)： THS8210PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁(yè)數(shù)： 8/73頁(yè)
文件大?。?/td> 2053K
代理商： THS8210PFP
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
16
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
The table summarizes all supported video mode configurations.
Each video mode is characterized by three attributes:
-
input interface: data is accepted over 10, 20 or 30 bit interface (or 8,16,24 bit interface for 8-bit data when
using 8 MSB’s of each input data bus and connecting 2 LSB’s to ground). This selection is controlled by
register ‘dman_cntl’.
-
timing control: video timing is either embedded in the datastream or supplied via dedicated timing signals.
In
the latter case additional Hsync (HS_IN), Vsync (VS_IN) and FieldID (FID) input signals are required to
synchronize the video data source and THS8200 in the case of ‘slave timing mode’. This selection is controlled
by register ‘dtg2_embedded_timing’.
-
synchronization: video timing is either supplied to the device (slave) or THS8200 requests video data from the
source (master). This selection is controlled by register ‘chip_ms’.
Note: device operation with combinations of register settings for ‘dman_cntl’, ‘dtg2_embedded_timing’ and
‘chip_ms’ that result in operating modes not marked in the table above, is not guaranteed. See detailed register
map description for actual register settings.
Furthermore the table shows for which modes
presets are defined. When in a preset video mode, the
(linetype/breakpoint)-pairs that define the frame format (see discussion of DTG) are pre-programmed. Therefore
the user does not need to define the table with linetype/breakpoint settings, nor does the field and framesize need
to be programmed. However, when in preset mode, still the horizontal parameters (all ‘dtg1_spec_x’ registers for
the linetypes used by the preset setting, and ‘dtg1_total_pixels’ registers) need to be programmed. Presets are
available for most popular video DTV video formats. Alternatively generic modes for SDTV, HDTV or VESA can be
selected, which allow full programmability of the field/frame sizes and DTG parameters.
Note from the table that:
-
If embedded timing is used, the device is always in slave mode since the datastream supplied to THS8200/10
contains the video timing information.
-
Master operation is only supported for PC graphics (VESA) formats.
-
In HDTV modes with embedded timing, data is supplied to the device over a 20 bit interface, as defined in
SMPTE274/296M.
-
In SDTV modes with embedded timing, data is supplied to the device over a 10 bit interface. When the video
format is interlaced, this interface is known as ITU-R.BT656 (525I,625I). When the video format is progressive,
only 525P is supported with embedded timing. 625P can be supported with dedicated timing, using the SDTV
generic mode.
-
In generic modes with dedicated timing, both 20 bit (4:2:2) and 30 bit (4:4:4) are supported.
-
In PC graphics modes (VESA generic), input data is either over the 30-bit interface or over the 16/15-bit
interface and always has dedicated timing. Note that the 16 bit interface is NOT equivalent to a 2x8-bit version
of the 20-bit interface, see next section on input interface formats for details.
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