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參數(shù)資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 66/73頁 |
| 文件大小： | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
69
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
[0000000000]
Sets the width of the VS_OUT output signal during
the vertical blank interval of field 2 in interlaced video
modes. In progressive video modes, this register
must be set to all ‘0’.
dtg2_vdly2(10:0):
VS_OUT delay, field 2
{dtg2_vlength2_msb_vdly2_msb 0x77(2:0) &
dtg2_vdly2_lsb 0x78(7:0)}
[11111111111]
Sets the line number that the VS_OUT signal is
asserted on for field 2 of interlaced scan video
modes. For progressive scan video modes, this
register must be set to all ‘1’.
dtg2_hs_in_dly(12:0): DTG horizontal delay
{dtg2_hs_in_dly_msb 0x79(4:0) &
dtg2_hs_in_dly_lsb 0x7A(7:0)}
[0000000111101]
Sets the number of pixels that the DTG startup is
horizontally delayed with respect to “HS” input for
dedicated timing modes or “EAV” input for embedded
timing modes.
Note: it is possible to delay startup past the end of a
line when this delay is programmed higher than the
total number of pixels per line.
dtg2_vs_in_dly(10:0): DTG vertical delay
{dtg2_vs_in_dly_msb 0x7B(2:0) &
dtg2_vs_in_dly_lsb 0x7C(7:0)}
[00000000011]
Sets the number of lines that the DTG startup is
vertically delayed with respect to “VS” input for
dedicated timing modes or the line counter value for
embedded timing.
Note: it is possible to delay startup past the end of a
frame when this delay is programmed higher than the
total number of lines per frame.
dtg2_rgb_mode_on:
RGB/YPbPr mode
selection
{dtg2_cntl 0x82(6)}
[1]
This selection affects the relative blank vs video level
position: on R,G,B & Y channels an offset will be
added to the DAC outputs
0 : YPbPr mode (blanking at bottom range for Y –
midrange for Pb,Pr channels)
1 : RGB mode (blanking at bottom ranges for all
channels)
dtg2_embedded_timing:
Video Sync input source
{dtg2_cntl 0x82(5)}
[0]
0 : Timing of video input bus is derived from
HS,VS,FID dedicated inputs
1 : Timing of video input bus is assumed embedded
in video data using SAV/EAV code sequences.
dtg2_vsout_pol:
VS_OUT polarity
{dtg2_cntl 0x82(4)}
[1]
0 :
Positive polarity
1 :
Negative polarity
dtg2_hsout_pol:
HS_OUT polarity
{dtg2_cntl 0x82(3)}
[1]
0 : Negative polarity
1 : Positive polarity
dtg2_fid_pol:
FID polarity
{dtg2_cntl 0x82(2)}
[1]
0 : Negative polarity
1 : Positive polarity
dtg2_vs_pol:
VS_IN polarity
{dtg2_cntl 0x82(1)}
[1]
0 : Negative polarity
1 : Positive polarity
dtg2_hs_pol:
HS_IN polarity
{dtg2_cntl 0x82(0)}
[1]
0 : Negative polarity
1 : Positive polarity
CGMS Control (sub-addresses 0x83-0x85)
cgms_macrovision_en:
Macrovision
TM 525P enable
(THS8210 only)
{cgms_cntl_header 0x83(7)}
[0]
0 : No Macrovision
TM copy protection on DAC outputs
in 525P mode.
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