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| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 57/73頁 |
| 文件大?。?/td> | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
60
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
Register descriptions
Legend: Between { } are shown the name(s),
subaddress(es) and bit position(s) where each
register can be found in the register map.
The default register value is shown between [ ] in
binary format, and hexadecimal (h) and/or decimal(d)
notation where listed.
System control (sub-addresses 0x02-0x03)
ver(7:0):
Device version
{version 0x02(7..0)}
[00000000]
The user can read this register to find out which
version of THS8200 is in the system.
vesa_clk:
Clock mode selection
{chip_ctl 0x03(7)}
[0]
0 : Normal operation
1 : All clocks become identical, except for the half
rate clock, and the DLL is bypassed. This is used in
VESA mode in order to support a direct 205MHz
input clock. No internal 2x interpolation is available.
This mode should be used for all formats that require
a >80MSPS pixel clock since the internal DLL for 2x
clock generation is guaranteed only up to 80MSPS.
The half-rate clock is still internally generated if
needed to allow e.g. 148MHz 20-bit input (1080P).
dll_bypass:
DLL bypass
{chip_ctl 0x03(6)}
[0]
0 : DLL used for clock generation; normal operation
with internally generated 2x clock. This mode should
be selected for most modes when a 1x clock is
available on the device clock input, and either 1x or
2x DAC operation is desired internally (as selected
by register data_ifir35_bypass)
1 : DLL bypassed for clock generation. In this case
the clock input on the CLKIN pin is directly used as
the 2x clock, rather than the internally generated
signal from the DLL. This mode is meant for test
purposes only.
vesa_colorbars:
Color bar test pattern
{chip_ctl 0x03(5)}
[0]
0 : normal operation
1 : Device generates color bar pattern; external video
inputs are ignored. The color bar pattern is only
supported in VESA PC graphics mode, with the
device configured in master mode (chip_ms=1).
dll_freq_sel:
DLL frequency range
select
{chip_ctl 0x03(4)}
[0]
Sets a frequency range for the DLL 2x clock
generation. The DLL should not be used at >80MHz.
In this case ‘vesa_clk’ should be enabled. As a
consequence 2x video interpolation is not available
for formats with >80MHz pixel clock.
0 : high frequency range: pixel clock from 40-80MHz
1 : low frequency range: pixel clock from 10-40MHz
dac_pwdn:
DAC powerdown
{chip_ctl 0x03(3)}
[0]
0 : normal operation
1 : DACs go into powerdown state.
chip_pwdn:
Chip powerdown
{chip_ctl 0x03(2)}
[0]
0 : normal operation
1 : powerdown of all digital logic except I2C
chip_ms:
Chip mode select
{chip_ctl 0x03(1)}
[0]
0 : slave mode. Device will synchronize to incoming
video sync signals, either embedded in ITU-R.BT656
interface or received from dedicated timing signals.
1 : master mode. Device will request video data and
generate video input timing signals to external
(memory) device, according to the programmed
frame/field format. Master mode is only available
when the DTG is operating in VESA mode (PC
graphics signals).
arst_func_n:
Chip software reset
{chip_ctl 0x03(0)}
[1]
0 : functional block goes into reset state. I2C
registers retain values.
Note: the user needs to issue a software reset after
input video is disconnected from the input bus and
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