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參數(shù)資料
| 型號： | THS8210PFP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | POWER, PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 41/73頁 |
| 文件大?。?/td> | 2053K |
| 代理商： | THS8210PFP |
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THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
46
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
D/A conversion
THS8200/10 contains 3 DAC’s with an internal resolution of 11 bits, and max. speed of 205MSPS. This allows
operation with all (H)DTV formats including 1080P, and PC graphics formats up to UXGA@75Hz.
The DAC output compliance can be selected between two full-scale ranges using the register ‘data_fsadj’.
DIGMUX will select DTG output data during non-video linetypes, except when ‘dtg1_passthrough’ is active: in this
case video input data will still be passed during active video portion of certain linetypes, as identified in the prior
section on the DTG linetypes.
THS8200/10 supports output in either RGB or YPbPr color spaces. When using RGB output, register
‘dtg2_rgb_mode_on’ needs to be set. In this case an offset is added to all DAC output channels in order to provide
headroom for the negative sync. Nominally the blanking level is at 350mV, and the 700mV swing extends upwards.
Therefore peak white corresponds to 1.35V. When YPbPr mode is selected on this register, the offset is only
added to the Y channel output; Pb and Pr outputs now have a video range from 0 to 700mV with 0V corresponding
to internal DAC input code 0 (note that due to the CSM block this could correspond to another device input code).
The Pb,Pr chroma difference channels are thus assumed to be offset binary encoded, not 2’s complement.
Finally the DTG mode will determine whether the DIGMUX will switch in output data from the DTG: e.g. in VESA
mode the DACs will always be driven by the video input bus. When the DTG overrides the the video input bus in
SDTV or HDTV modes, the actual amplitude levels output by the DACs during this time are user-programmable via
registers ‘dtg1_<y,cbcr>_blank’, ‘dtg1_<y,cbcr>_sync_low’ and ‘dtg1_<y,cbcr>_high’.
We will next outline some of the analog component video output formats that can be generated from THS8200/10.
RGB output without sync signal insertion / general purpose application DAC
In this mode, no sync signal is inserted on any of the analog outputs. HS_OUT and VS_OUT signals are generated
for output video synchronization. This mode is commonly used in computer graphics video output.
Two levels of full-scale output can be selected by software. For video applications, the nominal voltage levels are
0.7V and 1.305V. The 0.7V level is used in component video display; 1.305V is used in NTSC/PAL composite
video display. For composite video applications, the digital video stream needs to be encoded in an external device
according to either NTSC or PAL standard. The figure below illustrates analog outputs without sync insertion.
When THS8200/10 is programmed in this mode, it can also be used as a general-purpose DAC due to the linear
response to the DAC input codes. Optionally the CSM block can be bypassed to avoid any processing on the
device input codes.
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