THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303 DALLAS TEXAS 77265
50
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
The blanking level of all channels is at 350mV. Note that for Pb and Pr output channels, there is no DC offset
added so DAC input code 0 now corresponds to 0V DC output. Whether or not offset is added to the DAC outputs
is determined from register setting ‘dtg2_rgb_mode_on’.
SMPTE compatible YPbPr output with sync signal inserted on all channels
In this mode, sync signals are inserted on all three channels Y, Cr and Cb. The Y channel output is identical to
before. The Pb,Pr channel outputs are shown below. The range of input code to Y channel is from 64 to 940. The
range of input code of CrCb channels is from 64 to 960.
The AC dynamic range during active video period is the same on all channels: 700 mV. But the corresponding
input code ranges are different. The input code range of Y is from 64 to 940; the input code range of Cr and Cb is
64 to 960. This means that two different code ranges are mapped to a same analog output range. Since three
DACs in THS8200 share a common full-scale adjust resistor, therefore, different input codes to the DAC will result
in different analog outputs. In order to map two code ranges into a same analog output, the input code range
should be scaled in the CSM block.