參數(shù)資料
型號： THS8210PFP
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： POWER, PLASTIC, TQFP-80
文件頁數(shù)： 62/73頁
文件大?。?/td> 2053K
代理商： THS8210PFP
THS8200/8210
‘ALL-FORMAT’ OVERSAMPLED COMPONENT VIDEO/PC GRAPHICS D/A SYSTEM WITH
THREE 11 BIT DAC’S, CGMS DATA INSERTION AND 525P MACROVISION
TM COPY
PROTECTION
SLES032—6/18/02 3:33 PM
POST OFFICE BOX 655303
DALLAS TEXAS 77265
65
Copyright 2001 Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products
without notice.
dtg1_spec_k(10:0):
End of active video to
sync (SDTV) / end of broad
pulse to sync (HDTV)
{dtg1_spec_k_msb 0x30(2:0) & dtg1_spec_k_lsb
0x2F(7:0)}
[00001011000] = [88d]
Distance from end of active video to leading edge of
sync (SDTV) or from end of broad pulse to negative-
to-positive transition of tri-level sync (HDTV)
dtg1_spec_k1(7:0):
End of active video in 1
st
half of line to center
equalization pulse (SDTV)
{dtg1_spec_k1 0x31(7:0)}
[00000000]
Distance from end of active video in 1
st half of line to
center equalization pulse for SDTV line type
ACTIVE_NEQ
dtg1_spec_g(11:0):
of linelength (SDTV)
{dtg1_spec_g_msb 0x33(3:0) & dtg1_spec_g_lsb
0x32(7:0)}
[000001011000] = [88d]
Half the line length. Only used in the calculations of
SDTV linetypes.
dtg1_total_pixels(12:0):
Total pixels per line
(SDTV/HDTV/VESA)
{dtg1_total_pixels_msb 0x34(4:0) &
dtg1_total_pixels_lsb 0x35(7:0)}
[0010100100000] = [1312d]
Total number of pixels per line. Used in all DTG
modes.
dtg1_field_flip:
FID/F polarity select
{dtg1_fieldflip_linecnt_msb 0x36(7)}
[0]
0 : DTG is initialized to field1 at active VS edge when
a ‘0’ is received on FID signal or F bit.
1 : DTG is initialized to field1 at active VS edge when
a ‘1’ is received on FID signal or F bit.
dtg1_linecnt(10:0):
DTG start line number
{dtg1_fieldflip_linecnt_msb 0x36(2:0) &
dtg1_linecnt_lsb 0x37(7:0)}
[00000000001]
Sets the starting line number for the DTG when
Vsync input or V-bit is asserted (vertical display
control)
dtg1_on:
DTG on/off
{dtg1_mode 0x38(7)}
[1]
0 : DTG output held to dtg_y_blank value
1 : DTG on
dtg1_pass_through:
DTG pass-through
{dtg1_mode 0x38(4)}
[0]
0 : Video data blocked during certain linetypes.
1 : Video data passed during certain linetypes.
See description of linetypes in functional description
for details.
dtg1_mode(3:0):
DTG mode selection
{dtg1_mode 0x38(3:0)}
[0110]
Selects the operation mode of the DTG according to
table below. Each setting is either an SDTV, HDTV or
VESA format, as shown:
dtg1_mode
Mode
0000
ATSC MODE 1080P (SMPTE 274M
Progressive) [HDTV]
0001
ATSC MODE 1080I (SMPTE274M
Interlaced) [HDTV]
0010
ATSC MODE 720P (SMPTE296M
Progressive) [HDTV]
0011
Generic mode for HDTV [HDTV]
0100
ATSC MODE 480I (SDTV 525 lines
Interlaced) [SDTV]
0101
ATSC MODE 480P (SDTV 525 lines
progressive) [SDTV]
0110
VESA MASTER [VESA]
0111
VESA SLAVE [VESA]
1000
SDTV 625 Interlaced [SDTV]
1001
Generic mode for SDTV [SDTV]
Others
[Null]
dtg1_frame_size(10:0):Generic mode frame size
{dtg1_frame_field_size_msb 0x39(6:4) &
dtg1_framesize_lsb 0x3A(7:0)}
[01100000000]
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