參數(shù)資料
型號(hào)： TS68230CFN8
廠商： 意法半導(dǎo)體
英文描述： HMOS PARALLEL INTERFACE/TIMER
中文描述： HMO的并行接口/定時(shí)器
文件頁(yè)數(shù)： 17/61頁(yè)
文件大小： 2911K
代理商： TS68230CFN8
2.3. DIRECT METHOD OF RESETTING STATUS
In certain modes one or more handshake pins can
be used as edge-sensitive inputs for the sole pur-
pose of setting bits in the port status register. These
bits consist of simple flip-flops. They are set (to one)
by the occurrence of the asserted edge of the
handshake pin input. Resetting a handshake status
bit can be done by writing an 8-bit mask to the port
status register. This is called the direct method of re-
setting. To reset a status bit that is resettable by the
direct method, the mask must contain a one in the
bit position of the port status register corresponding
to the desired status bit. For status bits that are not
resettable by the direct method in the chosen mode,
the data written to the port status register has no ef-
fect. For status bits that are resettable by the direct
method in the chosen mode, a zero in the mask has
no effect.
2.4. HANDSHAKE PIN SENSE CONTROL
The PI/T contains exclusive-OR gates to control the
sense of each of the handshake pins, whether used
Figure 2.4 :
DMAREQ Associated with Input
Transfers.
V000313
as inputs or outputs. Four bits in the port general
control register may be programmed to determine
whether the pins are asserted in the low- or high-
voltage state. As with other control registers, these
bits are reset to zero when the RESET pin is asser-
ted, defaulting the asserted level to be low.
2.5. ENABLING PORTS A AND B
Certain functions involved with double-buffered da-
ta transfers, the handshake pins, and the status bits
may be disabled by the external system or by the
programmer during initialization. The port general
control register contains two bits, H12 enable and
H34 enable, which control these functions. These
bits are cleared to the zero state when the RESET
pin is asserted, and the functions are disabled. The
functions are the following :
1. Independent of other actions by the bus mas-
ter or peripheral (via the handshake pins), the
PI/T’s disabled handshake controller is held to
the "empty" state ; i.e., no data is present in the
double-buffered data path.
2. When any handshake pin is used to set a sim-
ple status flip-flop, unrelated to double-buffe-
red transfers, these flip-flops are held reset to
zero (see table 1.1).
3. When H2(H4) is used in an interlocked or pul-
sed handshake with H1(H3), H2(H4) is held
negated, regardless of the chosen mode, sub-
mode, and primary direction. Thus, for double-
buffered input transfers, the programmer may
signal a peripheral when the PI/T is ready to
begin transfers by setting the associated
handshake enable bit to one.
2.6. PORT A AND B ALTERNATE REGISTERS
In addition to the port A and B data registers, the PI/T
contains port A and B alternate registers. These re-
gisters are read only, and simply provide the ins-tan-
taneous (non-latched) level of each port pin. They
have no effect on the operation of the hand-shake
pins, double-buffered transfers, status bits, or any o-
ther aspect of the PI/T, and they are mode/submode
independent. Refer to
4.7. Port Alternate Regis-
ters
for further information.
TS68230
17/61
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