
counter preload register or continues counting when zero detect is reached ; bit 3 is unused and is read as zero
; bits 2 and 1 configure the path from the CLK and TIN pins to the counter controller ; and bit 0 ena-bles the timer.
This register is readable and writable at all times. All bits are cleared to zero when the RESET pin is asserted.
TCR
7 6 5
0 0 X
0 1 X
TOUT/TIACK Control
The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
The dual-function pin PC3/TOUT carries the TOUT function. In the run state it is used as a square-
wave output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dual-
function pin PC7/TIACK carries the PC7 function.
The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
5.1.3. Timer Interrupt Acknowledge Cycles
for details.
The dual-function pin PC3/TOUT carries the TOUT function and is used as a timer interrupt request
output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt ac-
knowledge input. Refer to the
5.1.3. Timer Interrupt Acknowledge Cycles
for details. This combi-
nation supports vectored timer interrupts.
The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-func-
tion pin PC7/TIACK carries the PC7 function.
The dual-function pin PC3/TOUT carries the TOUT function and is used as a timer interrupt request
output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are sup-
ported.
1 0 0
1 0 1
1 1 0
1 1 1
TCR
4
0
Zero Detect Control
The counter is loaded from the counter preload register on the first clock to the 24-bit counter after
zero detect, then resumes counting.
The counter rolls over on zero detect, then continues counting.
1
TCR
3
Unused and is always read as zero.
TCR
2 1
0 0
Clock Control
The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The
prescaler is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented,
rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
to $1F. The timer enable bit determines whether the timer is in the run or halt state.
The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
the timer is in the halt state.
The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
0 1
1 0
TS68230
41/61