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參數(shù)資料
| 型號： | TS68230CFN8 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時(shí)器 |
| 文件頁數(shù)： | 8/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230CFN8 |
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1.2.3. READ/WRITE (R/W). R/W is a high impe-
dance read/write input signal from the TS68000 bus
master, indicating whether the current bus cycle is
a read (high) or write (low) cycle.
1.2.4. CHIP SELECT (CS). CS is a high-impedance
input that selects the PI/T registers for the current
bus cycle. Address strobe and the data strobe (up-
per or lower) of the bus master, along with the ap-
propriate address bits, must be included in the
chip-select equation. A low level corresponds to an
asserted chip select.
1.2.5.
(DTACK). DTACK is an active low output that si-
gnals the completion of the bus cycle. During read
or interrupt acknowledge cycles, DTACK is asserted
after data has been provided on the data bus ; during
write cycles it is asserted after data has been accep-
ted at the data bus. Data transfer acknowledge is
compatible with the TS68000 and with other
TS68000 bus masters such as the 68440 direct me-
mory access controller (DMAC). A pullup resistor is
required to maintain DTACK high between bus cy-
cles.
DATA
TRANSFER
ACKNOWLEDGE
1.2.6. RESET (RESET). RESET is a high-impe-
dance input used to initialize all PI/T functions. All
control and data direction registers are cleared and
most internal operations are disabled by the asser-
tion of RESET (low).
1.2.7. CLOCK (CLK). The clock pin is a high-impe-
dance TTL-compatible signal with the same speci-
fications as the TS68000. The PI/T contains
dynamic logic throughout, and hence this clock must
not be gated off at any time. It is not necessary that
this clock maintain any particular phase relationship
with the TS68000 system clock. It may be connec-
ted to an independent frequency source (faster or
slower) as long as all bus specifications are met.
1.2.8. PORT A AND PORT B (PA0-PA7 AND PB0-
PB7). Ports A and B are 8-bit ports that may be
concatenated to form a 16-bit port in certain modes.
The ports may be controlled in conjunction with the
handshake pins H1-H4. For stabilization during sys-
tem power up, ports A and B have internal pullup re-
sistors to V
CC
. All ports pins are active high.
1.2.9. HANDSHAKE PINS (H1-H4). Handshake
pins H1-H4 are multi-purpose pins that (depending
on the operational mode) may provide an inter-
locked handshake, a pulsed handshake, an inter-
rupt input (independent of data transfers), or simple
I/O pins. For stabilization during system power up,
H2 and H4 have internal pullup resistors to V
CC
. The
sense of H1-H4 (active high or low) may be pro-
grammed in the port general control register bits
3-0. Independent of the mode, the instantaneous le-
vel of the handshake pins can be read from the port
status register.
1.2.10. PORT C (PC0-PC7/ALTERNATE FUNC-
TION). This port can be used as eight general pur-
pose I/O pins (PC0-PC7) or any combination of six
special function pins and two general purpose I/O
pins (PC0-PC1). Each dual-function pin can be a
standard I/O or a special function independent of the
other port C pins. When used as a port C pin, these
pins are active high. They may be individually pro-
grammed as inputs or outputs by the port C data di-
rection register. The dual-function pins are defined
in the following paragraphs.
The alternate functions TIN, TOUT, and TIACK are
timer I/O pins. TIN may be used as a rising-edge trig-
gered external clock input or an external run/halt
control pin (the timer is in the run state if run/halt is
high and in the halt state if run/halt is low). TOUT
may provide an active low timer interrupt request
output or a general-purpose square-wave output, i-
nitially high. TIACK is an active low high-impedance
input used for timer interrupt acknowledge.
Port A and B functions have an independent pair of
active low interrupt request (PIRQ) and interrupt ac-
knowledge (PIACK) pins.
The DMAREQ (direct memory access request) pin
provides an active low direct memory access con-
troller request pulse for three clock cycles, comple-
tely compatible with the 68440 DMAC.
TS68230
8/61
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