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參數(shù)資料
| 型號： | TS68230CFN8 |
| 廠商： | 意法半導體 |
| 英文描述： | HMOS PARALLEL INTERFACE/TIMER |
| 中文描述： | HMO的并行接口/定時器 |
| 文件頁數(shù)： | 48/61頁 |
| 文件大?。?/td> | 2911K |
| 代理商： | TS68230CFN8 |
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SECTION 6
ELECTRICAL SPECIFICATIONS
This section contains electrical specifications and associated timing information for the TS68230.
6.1 ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
IN
T
A
Parameter
Value
Unit
V
V
°
C
Supply Voltage
Input Voltage
Operating Temperature Range
TS68230C
TS68230V
Storage Temperature
– 0.3 to + 7.0
– 0.3 to + 7.0
T
L
to T
H
0 to + 70
– 40 to + 85
– 55 to + 150
T
stg
°
C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields ; however, it is
advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-
6.2 THERMAL DATA
θ
JA
Thermal Resistance Plastic
50
°
C/W
impedance circuit. Reliability of operation is enhanced if unu-
sed inputs are tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
CC
).
6.3. POWER CONSIDERATIONS
The average chip-junction temperature, T
J
, in
°
C
can be obtained from :
T
J
= T
A
+ (P
D
θ
JA
)
Where :
T
A
= Ambient Temperature,
°
C
θ
JA
= Package Thermal Resistance, Junction-to-
Ambient,
°
C/W
P
D
= P
INT
+ P
I/O
P
INT
= I
CC
x V
CC
, Watts - Chip Internal Power
P
I/O
= Power Dissipation on Input and Output Pins
-User Determined
For most applications P
I/O
< P
INT
and can be neglec-
ted.
An approximate relationship between P
D
and T
J
(if
P
I/O
is neglected) is :
P
D
= K (T
J
+ 273
°
C)
Solving equations 1 and 2 for K gives :
K = P
D
(T
A
+ 273
°
C) +
θ
JA
P
D2
Where K is a constant pertaining to the particular
part. K can be determined from equation 3 by mea-
suring P
D
(at equilibrium) for a known T
A
. Using this
value of K the values of P
D
and T
J
can be obtained
TS68230
48/61
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