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參數(shù)資料
| 型號： | TVP3010-85 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標，伽瑪校正貴賓（85MHz，高/寬光標，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 13/100頁 |
| 文件大?。?/td> | 571K |
| 代理商： | TVP3010-85 |
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1–7
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
62
SFLAG
I
(TTL
compatible)
Split shift-register-transfer flag. The TVP3010 VIP detects a low-
to-high transition on this terminal during a blank sequence and
immediately generates an SCLK pulse. This early SCLK pulse
replaces the first SCLK pulse in the normal sequence.
System blank input. SYSBL is active (low).
SYSBL
60
I
(TTL
compatible)
HSYNC,
VSYNC
58, 59
I
(TTL
compatible)
Horizontal and vertical sync inputs. These signals are used to
generate the sync level on the green current output. They are active
(low) inputs, but the HSYNCOUT and VSYNCOUT outputs can be
programmed through general control register.
Video clock output. VCLK is the user-programmable output for
synchronization to graphics processor.
VCLK
78
O
(TTL
compatible)
VGABL
61
I
(TTL
capability)
VGA blank input. VGABL is active (low).
VGA(0–7)
65–72
I
(TTL
capability)
VGA pass-through bus. These buses can be selected as the pixel bus
for VGA mode, but it does not allow for any multiplexing.
VSYNCOUT
47
O
(TTL
capability)
Vertical sync output after pipeline delay. For system mode, the output
can be programmed but for the VGA mode, the output carries the
same polarity as the input.
WR
30
I
(TTL
capability)
I
(TTL
capability)
Write strobe input. A logic 0 on this terminal initiates a write to the
register map. As with RD, write transfers are asynchronous and
initiated on the low-going edge of WR, (see Figure 3–1).
DAC resolution selection or overscan input. This terminal is used to
select the data bus width (8 or 6 bits) for the DAC and is essentially
provided in order to maintain compatibility with the IMSG176. When
this terminal is a logical 1, 8-bit bus transfers are used with D7 the MSB
and D0 the LSB. For 6-bit bus operation, while the color palette still has
the 8-bit information D5 shifts to the bit 7 position with D0 shifted to the
bit 2 position and the two LSBs are filled with zeros at the output
multiplexer to DAC. The palette holding register zeroes the two MSBs
when it is read in the 6-bit mode. The terminal can also be configured
to function as the overscan input facilitating the creation of custom
screen borders. This terminal defaults to 8/6 after reset.
8/6 [OVS]
64
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
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