- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385951 > TVP3010-85 (Texas Instruments, Inc.) Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) PDF資料下載
參數(shù)資料
| 型號(hào)： | TVP3010-85 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板) |
| 中文描述： | 硬件光標(biāo)，伽瑪校正貴賓（85MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板） |
| 文件頁數(shù)： | 21/100頁 |
| 文件大?。?/td> | 571K |
| 代理商： | TVP3010-85 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
2–7
The output-clock-selection register is used to program the desired divided-down frequencies for the
reference/shift and video clocks.
Table 2–5. Output-Clock-Selection Register Format
OUTPUT-CLOCK-SELECTION-REGISTER BITS (see Note 4)
6
5
4
3
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
FUNCTION (see Notes 4 5 6 and 7)
FUNCTION (see Notes 4, 5, 6, and 7)
2
x
x
x
x
x
x
1
x
x
x
x
x
x
0
x
x
x
x
x
x
VCLK/1 output ratio
VCLK/2 output ratio
VCLK/4 output ration
VCLK/8 output ratio
VCLK/16 output ratio
VCLK/32 output ratio
1
1
0
x
x
x
VCLK/64 output ratio
VCLK output held at logic 1
1
1
1
x
x
x
x
x
x
0
0
0
RCLK/1 output ratio (see Notes 4 and 7)
x
x
x
0
0
1
RCLK/2 output ratio (see Notes 4 and 7)
x
x
x
0
1
0
RCLK/4 output ratio (see Notes 4 and 7)
x
x
x
0
1
1
RCLK/8 output ratio (see Notes 4 and 7)
x
x
x
1
0
0
RCLK/16 output ratio (see Notes 4 and 7)
x
x
x
1
0
1
RCLK/32 output ratio (see Notes 4 and 7)
x
x
x
1
1
0
RCLK/64 output ratio (see Notes 4 and 7)
RCLK/64, SCLK output held at logic 0
0
x
x
x
1
1
0
0
x
x
x
1
1
1
RCLK, SCLK outputs held at logic 0
x
1
1
1
1
1
1
Clock counter reset (6)
These lines indicate the reset conditions as required for VGA pass-through.
NOTES:
4. Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer. Register
bit 7 is a don’t care bit.
5. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before
the new clocks are stabilized and running.
6. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = logic 0, and VCLK = logic 1.
7. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.
2.3.2
The TVP3010 VIP has two pixel-data latching modes, allowing for flexibility in the frame-buffer interface
timing. For the pixel port [P(0–31)], data is always latched on the rising edge of LCLK. If auxiliary-control
register (ACR) bit 3 is set to logic 1 (default), the internal circuitry is configured for self-clocked mode. In this
mode, the RCLK or SCLK output of the palette must be used as the timing reference to present data to the
pixel port [P(0–31)]. In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can be a delayed
version of RCLK within the timing requirements of the TVP3010. The self-clocked mode of frame-buffer
latching is similar to the operation of the TLC3407X video interface palette devices.
Frame-Buffer Clocking: Self- or Externally Clocked
The internal TVP3010 blank signal is generated from either VGABL or SYSBL, depending on whether the
VGA port is enabled (multiplex-control register 2 (MCR2) bit 7 = logic 1) or disabled (MCR2 bit 7 = logic 0).
The rising edge of CLK0 is used to latch VGABL when the VGA port is enabled. The falling edge of VCLK
is used to sample and latch the SYSBL input when the VGA port is disabled. When the internal blank
becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when the sampled
SYSBL goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK then is held
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3010C | Video Interface Palette |
| TVP3010M | Video Interface Palette |
| TVP3020-175 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3020-135 | Video Interface PALETTE(視頻接口調(diào)色器) |
| TVP3025-135 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3010-85FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3010-85FNR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3010C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3010M | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3020 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。