![](http://datasheet.mmic.net.cn/390000/TVP3010-110_datasheet_16839157/TVP3010-110_47.png)
2–33
2.9.3
An ID register with a hardwired code is provided that can be used as a software verification for different
versions of the system design. The ID code in the TVP3010 palette is static and may be read without
consideration to the dot clock or video signals. The ID code is read through the indirect register map (see
Table 2–2). The value defined for the palette is 10 (hex).
2.10 MUXOUT [SENSE]Output
The MUXOUT [SENSE] terminal can be configured as MUXOUT or SENSE by programming bit 3 of the
configuration register (see Section 2.16.1). When the terminal is configured as MUXOUT, it can be used to
control external devices. MUXOUT is a TTL-compatible output that is software programmable by writing
configuration bit 2 through the TVP3010 microinterface. Its typical application is to control an external
multiplexer, selecting between the VGA pass-through and normal mode horizontal and vertical sync signals
supplied on the HSYNC and VSYNC inputs. This output is driven low at reset or when the VGA pass-through
mode is selected. At any other time, it can be programmed to the desired polarity via the configuration
register. The reset default is MUXOUT. See Section 2.9.2 for the detailed description of SENSE.
2.11 Reset
There are two ways to reset the TVP3010 palette:
Identification Code
Power-on reset
Software reset
The default register settings are detailed in Tables 2–1 and 2–2.
2.11.1
There is a power-on reset (POR) circuit built into the 32-bit TVP3010. This POR operates at power on only.
Even though this circuitry is provided, it is still recommended to utilize the software reset function as
described in Section 2.11.2 after the power supply has stabilized to ensure the reset condition. All registers
reset to VGA default settings.
2.11.2
Software Reset
When data is written to the reset register [FF (hex) on the indirect register map], all other registers are
initialized to VGA default settings accordingly. Any data may be written into the reset register to cause this
reset to occur.
2.12 Frame-Buffer Interface
The TVP3010 provides three output clock signals and one input clock signal for controlling the frame-buffer
interface: SCLK, RCLK, LCLK, and VCLK. SCLK can be used to clock out data from VRAM shift registers
directly. Split shift-register-transfer function is also supported. RCLK is provided so that pixel-port [P(0–31)]
data loading can be synchronized to the VRAM. LCLK rising edges latch data presented on the pixel port,
and VCLK is used to clock and synchronize the video control signals such as HSYNC, VSYNC, SYSBL.
Clocking of the frame-buffer interface (self-clocked and externally-clocked timing) is discussed in detail in
Section 2.3.2.
Power-On Reset
The 32-terminal interface allows many operational display modes as defined in Section 2.4 and Table 2–6.
The pixel latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which
multiple pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the
pixels that reside on the low-numbered pixel-port terminals. For example, in an 8-bit-per-pixel pseudo-color
mode with an 8:1 multiplex ratio, the pixel display sequence is P(0–7), P(8–15), P(16–23), and P(24–31).
The TVP3010 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register bit 3. See Sections 2.4.1 and 2.16.2, and Appendix C for details
of operation.