參數(shù)資料
型號： TVP3010-85
廠商： Texas Instruments, Inc.
英文描述： Hardware Cursor, GAMMA Correction VIP(85MHz,高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板)
中文描述： 硬件光標(biāo)，伽瑪校正貴賓（85MHz，高/寬光標(biāo)，伽馬校正，視頻接口調(diào)色板）
文件頁數(shù)： 51/100頁
文件大?。?/td> 571K
代理商： TVP3010-85
2–37
If the SSRT function is enabled but SFLAG is held low, the SCLK runs as if the SSRT function is disabled.
Since the SFLAG input is not qualified by the blank signal within the palette, it needs to be held low or
disabled any time the SSRT SCLK pulse is not intended. Refer to Section 2.3 and Figures 2–2 through 2–5
for more system details.
2.16 Control-Register Definitions
2.16.1
Configuration Register
The configuration register is used to control the dual function pins on the TVP3010 so that it can maintain
pin compatibility with the TLC3407x VIP parts. At reset, the configuration register defaults to TLC3407x
compatible pin settings. Bit 7 of the configuration register corresponds to data bus bit 7, index = 1E (hex).
Table 2–12. Configuration Register
BIT
NAME
VALUES
DESCRIPTION
CR7
X
Reserved undefined
Reserved, undefined
CR6
0: In phase (default)
VCLK polarity select specifies whether the VCLK signal is in phase or opposite
phase of the RCLK and SCLK signals.
1: Opposite phase
CR5
0: Internal RCLK (default)
LCLK source selects the LCLK source. If bit 5 = logic 0, (default) then LCLK is
internally connected to RCLK. If bit 5 = logic 1, then CLK4[LCLK] is configured
internally connected to RCLK. If bit 5 logic 1, then CLK4[LCLK] is configured
as the LCLK input and an external LCLK source must be supplied. See
Section 2.3.1.
1: CLK4[LCLK]
CR4
0: Disabled (default)
RCLK enable specifies whether RCLK is output on CLK3[RCLK]. If disabled,
then CLK3[RCLK] is CLK3. See Section 2.3.
1: Enabled
CR3
0: MUXOUT (default)
MUXOUT or SENSE selects MUXOUT or SENSE on MUXOUT[SENSE]. See
Sections 2.9 and 2.10.
1: SENSE
CR2
0: Low (default)
MUXOUT level terminal. If configuration register bit CR3 = logic 0, then this
terminal controls the logic level on MUXOUT.
1: High
CR1
0: 8/6 (default)
8/6 or OVS defines the terminal as 8/6 or OVS and controls the source of the
8/6 function signal. If CR1 = 0, then 8/6[OVS] is configured as the 8/6 terminal.
8/6 function signal. If CR1 0, then 8/6[OVS] is configured as the 8/6 terminal.
If CR1 = 1, then CR0 controls the 8/6 function and is configured as OVS. See
Sections 2.1 and 2.7.
1: OVS
CR0
0: 6-bit (default)
1: 8-bit (high)
8/6 level. When CR1 = logic 1, this bit controls the 8/6 operation. See
Section 2.1.
相關(guān)PDF資料
PDF描述
TVP3010C Video Interface Palette
TVP3010M Video Interface Palette
TVP3020-175 Video Interface PALETTE(視頻接口調(diào)色器)
TVP3020-135 Video Interface PALETTE(視頻接口調(diào)色器)
TVP3025-135 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3010-85FN 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3010-85FNR 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3010C 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3010M 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3020 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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