參數(shù)資料
型號(hào)： TVP3025-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁(yè)數(shù)： 11/99頁(yè)
文件大?。?/td> 663K
代理商： TVP3025-135
1–5
1.4
Ordering Information
TVP3025
– XXX
XXX
Pixel Clock Frequency Indicator
MUST CONTAIN THREE CHARACTERS:
–135: 135-MHz pixel clock
–175: 175-MHz pixel clock
–220: 220-MHz pixel clock
Package
MUST CONTAIN THREE LETTERS:
MDN: Metal, Quad Flat Pack
PCE:
Plastic, Quad Flat Pack (mechanical data unavailable at time of print)
1.5
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AVDD
CLK0
NO.
84, 86
Analog power. All AVDD terminals must be connected.
Dot clock 0 input. CLK0 can be selected to drive the dot clock at
frequencies up to 140 MHz. When VGA mode is active, the selected
clock source is CLK0. The maximum frequency in VGA mode is 85 MHz.
The maximum frequency for direct color/VGA switching in self-clocked
mode is 50MHz. This clock source is also selected at reset.
106
I
(TTL
compatible)
CLK1
107
I
(TTL
compatible)
Dot clock 1 input. CLK1 can be selected to drive the dot clock at
frequencies up to 140 MHz.
CLK2,
CLK2
108, 109
I
(TTL/ECL
compatible)
Dual-mode dot clock input. These inputs are essentially ECL-
compatible inputs, but two TTL clocks may be used on CLK2 and CLK2
if so selected in the input-clock-selection register. These inputs may be
selected as the dot clock up to the device limit while in the ECL mode
or up to 140 MHz in the TTL mode.
COMP1,
COMP2
77, 79
Compensation. COMP1 and COMP2 provide compensation for the
internal reference amplifier. A 0.1-
μ
F ceramic capacitor is required
between COMP1 and COMP2. This capacitor must be as close to the
device as possible for proper decoupling and to avoid noise pick up.
DCLK
122
O
Dot clock. Divided memory clock output. A frequency divided version of
the MCLK output.
DVDD
18, 45, 65,
117, 137, 143,
148
Digital power. All DVDD terminals must be connected.
D0–D7
47–54
I/O
(TTL
compatible)
MPU interface data bus. These terminals are used to transfer data in and
out of the register map and palette/overlay RAM.
FS ADJUST
76
I
Full-scale adjustment. A resistor connected between this terminal and
ground controls the full-scale range of the DACs.
GND
17, 46, 66, 69,
71, 73, 75, 83,
85, 118, 136,
142, 147
Ground. All GND terminals must be connected. The GNDs are
connected internally.
NOTE: All unused inputs should be tied to a logic level and not be allowed to float.
相關(guān)PDF資料
PDF描述
TVP3025-175 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-135PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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