參數(shù)資料
型號(hào)： TVP3025-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁(yè)數(shù)： 65/99頁(yè)
文件大?。?/td> 663K
代理商： TVP3025-135
2–51
color data. When writing color data, D6 and D7 are ignored. During color read cycles, D6 and D7 are logical
zeros. In the 6-bit mode, the TVP3025 full scale output current is about 1.5 percent lower than when in the
8-bit mode. This is because the 2 LSBs of each 8-bit DAC are logical zeros in the 6-bit mode. Accessing
the cursor RAM array does not depend on the resolution of the DACs.
2.4.5
The TVP3025 incorporates a power down capability, controlled by command bit CR00. While this command
bit is logic 0, the device functions normally. When this command bit is set to logic 1, the DACs are powered
down such that they output no current. If CR06 is taken to a logic 1 while CR00 is a logic 1, the internal dot
clock is halted. While in this sleep mode, the RAM and all registers still retain their data. Also, the MPU may
read or write to the RAM while the dot clock is running. The three command registers can still be written to
or read from by the MPU. The DACs require about 1 second to turn off or turn on, depending on the
compensation capacitor used.
Power Down Mode
2.4.6
The video RAM shift clock reference signal (RCLK) is generated by the TVP3025. RCLK is one sixteenth,
one eighth, one fourth, or one half the pixel clock rate, depending on whether multiplexing is 16:1, 8:1, 4:1,
or 2:1, respectively.
Frame Buffer Clocking
P0 – P63 are the pixel data inputs. They support different bits per pixel and multiplexing ratios as discussed
in Section 2.4.10. These pixel inputs are always latched on the rising edge of LCLK. The pixel clock is
specified to be either CLK0 or CLK1 by command bit CR24.
2.4.7
The TVP3025 provides an onboard clock doubler for high-speed, low cost operation. The clock doubler can
be enabled or disabled by programming bit CR33 in command register 3. At reset, the clock doubler is
disabled, but can be subsequently be enbled by programming CR33. Either CLK0 or CLK1 can be doubled
internally.
Onboard 2x TTL Clock Doubler
2.4.8
Pixel data is bit-wise logically ANDed with the contents of the pixel read-mask register during each pixel
clock cycle. The result is used to address the color palette RAM. In this way, bits can be enabled and disabled
from addressing the palette RAM. Pixel masking is enabled for all modes of operation, except where the
true color bypass is selected. The pixel read-mask register is not initialized and should be set to logic 1s for
proper operation.
Pixel Read-Mask Register
2.4.9
The 64-bit pixel port interface allows many operational display modes. For those multiplexed modes in which
multiple pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the
pixels that reside on the low numbered pixel port terminals. For example, in an 8-bit per pixel pseudo-color
mode with an 8:1 multiplex ratio, the pixel display sequence would be P(0–7), P(8–15), P(16–23),
P(24–31), P(32–39), P(40–47), P(48–55), and P(56–63).
Frame Buffer Pixel Port Interface
2.4.10
In addition to the standard modes provided by the 32-bit pixel port on the BT485, the TVP3025 has an
additional command register 4 to give access to its enhanced 64-bit pixel port. In general, for all of the
operating modes described in the following sections, if CR40 in command register 4 is set to a logic 1, 64-bit
pixel bus operation is assumed and all multiplex ratios are doubled.
Modes of Operation
2.4.10.1 4-Bits/Pixel Operation (8:1 or 16:1 Mux)
If the pixel port interface is operated as a 32-bit bus, it is multiplexed 8:1 and configured for 4 bits per pixel.
Alternatively, if CR40 is set to logic 1, then a 64-bit bus is assumed with multiplexing of 16:1 for 4 bits per
pixel. As a result, 8 or 16 independent 4-bit pixels are input to the device and latched on the rising edge of
相關(guān)PDF資料
PDF描述
TVP3025-175 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-135PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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