參數(shù)資料
型號(hào)： TVP3025-135
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
中文描述： 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器）
文件頁(yè)數(shù)： 66/99頁(yè)
文件大?。?/td> 663K
代理商： TVP3025-135
2–52
LCLK. One rising edge of LCLK should occur every eight dot clock cycles for a 32-bit bus (every 16 dot clock
cycles for a 64-bit bus). RCLK is automatically set when the multiplex mode is chosen such that its frequency
equals the selected dot clock frequency divided by the multiplex ratio (i.e., dot clock/8 or dot clock/16
depending on CR40). The 4 bits from each pixel selects 1 of 16 locations (RAM address 0–15) in the palette
in the order presented in Table 2–18.
2.4.10.2 8-Bits/Pixel Operation (4:1 or 8:1 Mux)
If a 32-bit wide pixel input port is selected, then the bits are multiplexed 4:1 and are configured for 8 bits per
pixel. If 64-bit wide operation is chosen, then the port is multiplexed 8:1 with 8 bits per pixel. One rising edge
of LCLK should occur every four dot clocks cycles for 32-bit port selection or every eight dot clocks cycles
for 64-bit port selection. RCLK automatically equals the dot clock divided by four or eight when the
multiplexing mode is selected. The 8 bits from each pixel selects 1 of 256 locations in the palette as shown
in Table 2–18.
2.4.10.3 16-Bits/Pixel Operation (2:1 or 4:1 Mux)
If a 32-bit bus is selected, the pixel inputs are multiplexed 2:1 and configured for 16 bits per pixel. If a 64-bit
bus is selected, the pixel inputs are multiplexed 4:1 and configured for 16 bits per pixel. One rising edge of
LCLK should occur every two or four dot clock cycles depending on pixel bus width. RCLK automatically
equals the dot clock divided by 2 or 4 depending on pixel bus width. Both 5:5:5 and 5:6:5 RGB color formats
are supported as shown in Table 2–18. With these modes, the display can contain 32 K or 64 K simultaneous
colors. The DACs can be configured for 6 or 8 bits of resolution in this mode.
Bit CR14 is used to enable or disable true color palette bypass. This bit should always be programmed to
a logic 1, since the TVP3025 only supports direct color (palette bypass) while in the BT485 mode. If true
color (gamma corrected) is desired, then it can be programmed through the TVP3025 indirect register mode.
Bit CR22 is used in the BT485 to program sparse or contiguous addressing. The TVP3025 only supports
sparse addressing, so this bit is nonfunctional, but can be written to or read from with no effect on circuit
operation.
2.4.10.4 24-Bit/Pixel Operation (1:1 or 2:1 Mux)
If 32-bit pixel bus width is chosen, then 24 bits per pixel are latched 1:1 with no multiplexing. If a 64-bit bus
is chosen, then the 24 bits per pixel are multiplexed 2:1. One rising edge of LCLK should occur every dot
clock cycle for 1:1 multiplexing and every two dot clock cycles for 2:1 multiplexing. The RGB color format
in this mode is 8:8:8. Again CR14 needs to be set to a logic 1, since only direct color is supported by the
TVP3025 in the BT485 mode. With 24-bit true color, 16.8 million simultaneous colors are possible. The
DACs should be configured for 8-bit operation in this mode (CR01 = logic 1).
相關(guān)PDF資料
PDF描述
TVP3025-175 Video Interface PALETTE(三PLL，視頻接口調(diào)色器)
TVP3030-175 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-220 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3025-135PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-175PCE 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220MDN 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3025-220PCE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
TVP3026 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
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