![](http://datasheet.mmic.net.cn/390000/TVP3025-135_datasheet_16839165/TVP3025-135_48.png)
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2.3.10.3 Color-Key-Switching Control
The TVP3025 supports color-key-switching modes in which color data from the direct-color and overlay or
VGA ports is compared to a set of user-definable color-key registers. Based on the outcome of the
comparison, either direct color, overlay, or VGA are displayed (see Note 22). High and low color-key
registers are provided for each color and overlay/VGA so that ranges of colors can be compared as opposed
to a single color value. The register bit definitions for the color-key OL/VGA (low, high), color-key red (low,
high), color-key green (low, high), and color-key blue (low, high) range registers are shown in Section 2.3.18.
The color-key function is controlled by the color-key-control register bits 0–4. This register definition is
shown in Section 2.3.18.12.
Color-key switching is performed according to the following equation:
COLOR–KEY = [(OL + CKC0)
×
(R + CKC1)
×
(G + CKC2)
×
(B + CKC3)]
⊕
CKC4
where: OL = 1
if
if
if
if
color-key OL/VGA low
≤
overlay or VGA (Note 22)
≤
color-key OL/VGA high
color-key red low
≤
direct color (RED)
color-key green low
≤
direct color (GREEN)
color-key blue low
≤
direct color (BLUE)
R = 1
G = 1
B = 1
≤
color-key red high
≤
color-key green high
≤
color-key blue high
then
if
if
COLOR–KEY = 1, overlay or VGA is displayed.
COLOR–KEY = 0, direct-color is displayed.
NOTES: 22. When the VGA port is activated (MCR2 bit 7 = 1), the color-key OL/VGA register (low,high) color
comparison is performed on VGA data and the VGA port is color-key switched. If the VGA port is not
activated (MCR2 bit 7 = 0) the comparison is performed on overlay data and overlay is color-key switched.
23. CKC0–CKC3 can be used to individually enable or disable certain colors in the comparison for maximum
flexibility. If color-key switching is not desired, CKC0–CKC3 should be set to logic 0. CKC4 is then used
to set the default for either direct color or palette graphics. The default condition at reset is CKC0 = CKC1
= CKC2 = CKC3 = logic 0 and CKC4 = logic 1. This causes the function to default to palette graphics as
required for VGA pass-through mode.
24. The color-key comparison for the overlay and VGA data is performed after the read mask and palette page
registers so that an 8-bit comparison can be performed. This also gives the maximum flexibility to the user
in performing the color comparisons. If the overlay defined for a given mode is less than 8 bits per pixel,
the data is shifted to the LSB locations and the palette-page register fills the remaining MSB positions.
25. For those direct-color modes that have less than 8 bits per pixel of red, green, and blue direct-color data,
the data is internally shifted to the MSB positions for each color and the remaining LSB bits are filled with
logic 0s before the 8-bit comparisons are performed.
26. The windowing and color-key functions are integrated such that if either SWITCH = 1 (windowing case, see
Section 2.3.10) or color key = 1, palette graphics are displayed (overlay or VGA depending on multiplex-
control register 2 bit 7) instead of direct-color data. Both functions must be correctly set for proper operation.
2.3.11
The TVP3025 provides the capability to produce a custom screen border using the overscan function. The
overscan function is enabled by general-control register (GCR) bit 6. The overscan color is user-
programmable by writing to the overscan color red, green, and blue registers in the indirect register map.
Overscan
If the overscan function is enabled (GCR6 = logic 1), then overscan color is displayed any time that OVS
is high and blank is low (active). Note that blank is the internal blank signal and can either be generated from
VGABL or SYSBL depending on the mode selected.
If overscan is enabled, then the blanking pedestal is imposed on the analog outputs when both OVS and
blank are low. If overscan is disabled, then the blanking pedestal occurs when blank is low. Blank can be
either SYSBL or VGABL depending on the state of multiplex-control register 2 bit 7.
If VGA is disabled, OVS is sampled the same as the SYSBL signal (either on VCLK or LCLK depending on
miscellaneous-control register bit 6). If VGA is enabled, then OVS is sampled on the rising edge of CLK0.