參數(shù)資料
型號: TVP3025-135
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE(三PLL,視頻接口調(diào)色器)
中文描述: 視頻接口盒(三鎖相環(huán),視頻接口調(diào)色器)
文件頁數(shù): 39/99頁
文件大?。?/td> 663K
代理商: TVP3025-135
2–25
Table 2–9. Pseudo-Color Mode Pixel-Latching Sequence (see Note 15)
v1
s1
P0
s2
P0
s3
P0
s4
P0
s5
P0
s6
s7
VGA7–VGA0
P1, P0
P1–P0
P1
P1
P1
P1
P1
P3, P2
P3–P2
P2
P2
P7
P2
P15
P2
P31
P2
P63
P5–P4
P3
P7–P6
s8
s9
s10
s11
s12
s13
s14
s15
P1–P0
P1–P0
P1–P0
P3–P0
P3–P0
P3–P0
P3–P0
P3–P0
P3–P2
P3–P2
P3–P2
P7–P4
P7–P4
P7–P4
P7–P4
P5–P4
P15–P14
P5–P4
P31–P30
P5–P4
P63–P62
P11–P8
P11–P8
P31–P28
P11–P8
P63–P60
P15–P12
s16
P7–P0
s17
P7–P0
s18
P7–P0
s19
P7–P0
P15–P8
P15–P8
P15–P8
P23–P16
P23–P16
P63–P56
P31–P24
NOTE 15: The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups of data are
latched, the LCLK rising edge latches all the groups and the pixel clock shifts them out starting with the
low-numbered group. For example, in pseudo-color submode 3 with a 16-bit pixel bus width, the rising edge
of LCLK latches all the data groups shown above (s13) and the pixel clock shifts them out in the order P(3–0),
P(7–4), P(11–8), and P(15–12). Note that each line in each subtable above represents one pixel.
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