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參數(shù)資料
| 型號： | TVP3025-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 20/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-135 |
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2–6
2.2
Operation of a color palette access is essentially identical for both the TVP3020 and BT485 modes. The
color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM. This
register is automatically incremented following a RAM transfer, allowing the entire palette to be read/written
with only one access of the address register. When the address register increments beyond the last location
in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM are asynchronous
to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not cause any
noticeable disturbance on the display.
Color Palette
The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since a MPU access is eight
bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen (8/6 = 0).
If the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.
However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with IMSG176 and
Bt476. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs with 0s
after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC
calculation both take data after the output multiplexer, enabling total system verification (TVP3020 modes
only). The color palette access is described in the following two sections, and it is fully compatible with
IMSG176/8 and Bt476/8.
2.2.1
To load the color palette, the MPU must first write to the address register (write mode) with the address where
the modification is to start. This is then followed by three successive writes to the palette holding register
with 8 bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are
concatenated into a 24-bit word that is then written to the RAM location specified by the address register.
The address register then increments to the next location, which the MPU can modify by simply writing
another sequence of red, green, and blue data. A block of color values in consecutive locations can be
written to by writing the start address and performing continuous red, green, and blue write cycles until the
entire block has been written.
Writing to Color-Palette RAM
2.2.2
Reading from the palette is performed by writing to the address register (read mode) with the location to be
read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (6 or 8 bits depending on the 8/6 mode) for the specified location. Following the blue read cycle,
the contents of the color-palette RAM at the address specified by the address register are copied into the
holding register and the address register is again incremented. As with writing to the palette, a block of color
values in consecutive locations may be read by writing the start address and performing continuous red,
green, and blue read cycles until the entire block has been read. Since the color-palette RAM is dual ported,
the RAM may be read during active display without disturbing the video.
Reading From Color-Palette RAM
2.2.3
The pixel read-mask register is an 8-bit register used to enable or disable a bit plane from addressing the
color-palette RAM in the pseudo-color modes. Each palette address bit is logically ANDed with the
corresponding bit from the pixel read-mask register before going to the palette-page register (TVP3020
mode only) and addressing the palette RAM.
Read Masking
相關(guān)PDF資料 |
PDF描述 |
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| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
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| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-135PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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