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參數(shù)資料
| 型號： | TVP3025-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 26/99頁 |
| 文件大小： | 663K |
| 代理商： | TVP3025-135 |
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2–12
Table 2–7. Output-Clock-Selection Register Format
OUTPUT-CLOCK-SELECTION-REGISTER BITS (see Note 3)
6
5
4
3
x
0
0
0
FUNCTION
2
x
1
x
0
x
(see Notes 3, 4, 5, 6, and 7)
VCLK/1 output ratio
x
0
0
1
x
x
x
VCLK/2 output ratio
x
0
1
0
x
x
x
VCLK/4 output ration
x
0
1
1
x
x
x
VCLK/8 output ratio
x
1
0
0
x
x
x
VCLK/16 output ratio
x
1
0
1
x
x
x
VCLK/32 output ratio
x
1
1
0
x
x
x
VCLK/64 output ratio
VCLK output held at logic 1
x
1
1
1
x
x
x
1
x
x
x
0
0
0
RCLK/1 output ratio
1
x
x
x
0
0
1
RCLK/2 output ratio
1
x
x
x
0
1
0
RCLK/4 output ratio
1
x
x
x
0
1
1
RCLK/8 output ratio
1
x
x
x
1
0
0
RCLK/16 output ratio
1
x
x
x
1
0
1
RCLK/32 output ratio
1
x
x
x
1
1
0
RCLK/64 output ratio
RCLK/64, SCLK output held at logic 0
0
x
x
x
1
1
0
x
x
x
x
1
1
1
RCLK, SCLK outputs held at logic 0
x
1
1
1
1
1
1
Clock counter reset
These lines indicate the RESET conditions as required for VGA pass-through mode.
NOTES:
3. Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer.
4. Register bit 7 is used for 64-bit BT485 emulation. It is equivalent to BT485 mode command register
CR40 (see Section 2.4.15.5). When CR40 is set to logic 1, register bit 7 is set to logic 1, further dividing
the RCLK and SCLK by 2. In TVP3025 mode, it should be set to logic 0.
5. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before the
new clocks are stabilized and running.
6. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = logic 0, and VCLK = logic 1.
7. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.
2.3.6
Frame-Buffer Interface
The TVP3025 provides three output clock signals and one input clock signal for controlling the frame-buffer
interface: SCLK, RCLK, LCLK, and VCLK. Clocking of the frame buffer interface is discussed in Section
2.3.7. The 64-terminal interface allows many operational display modes as defined in Section 2.3.8 and
Table 2–8. The pixel latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes
in which multiple pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with
the pixels that reside on the low numbered pixel port terminals. For example, in an 8-bit-per-pixel
pseudo-color mode with an 8:1 multiplex ratio, the pixel display sequence is P(0–7), P(8–15), P(16–23),
P(24–31), P(32–39), P(40–47), P(48–55), and P(56–63).
The TVP3025 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This
can be controlled by general-control register bit 3. See Sections 2.3.8.1 and 2.16.1, and Appendix C for
details of operation.
2.3.7
Frame-Buffer Clocking
The TVP3025 provides SCLK and RCLK, allowing for flexibility in the frame buffer interface timing. For the
pixel port (P0–P63), data is always latched on the rising edge of LCLK. If auxiliary control register bit 3 is
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