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參數(shù)資料
| 型號： | TVP3025-135 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| 中文描述： | 視頻接口盒（三鎖相環(huán)，視頻接口調(diào)色器） |
| 文件頁數(shù)： | 64/99頁 |
| 文件大?。?/td> | 663K |
| 代理商： | TVP3025-135 |
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2–50
2.4
As discussed in Sections 2.1.1 and 2.1.2, the TVP3025 can be reset and initialized to a BT485 mode of
emulation. Table 2–2 lists the BT485 emulation register map. In general, register translations are
transparent to the user. An additional command register four is added to provide access to the enhanced
features that the TVP3025 provides beyond the BT485. Because of the use of register emulation, operation
of the device appears essentially identical to the BT485.
Circuit Description Using BT485 Register Emulation
The MPU interface and reading/writing of the color palette operations are covered in Section 2.2, since
operation is the same as in the TVP3020 mode.
2.4.1
To write cursor color data, the MPU writes the address register (cursor color write mode) with the address
of the cursor color location to be modified. The MPU performs three successive write cycles (8 bits each
of red, green, and blue), using RS0 – RS4 to select the cursor color registers. After the blue write cycle, the
3 bytes of red, green, and blue color information are concatenated into a 24-bit word and written to the cursor
color location specified by the address register. The address register then increments to the next location,
which the MPU can modify by writing another sequence of red, geen, and blue data. A block of color values
in consecutive locations can be written to by writing the start address and performing continuous RGB write
cycles until the entire block has been written. The address register (write mode) should be written with xx00
for overscan, xx01 for cursor color 0, and xx10 for cursor color 1.
Writing Cursor and Overscan Color Data
2.4.2
To read cursor color data, the MPU loads the address register (cursor color read mode) with the address
of the cursor color location to be read. The contents of the cursor color register at the specified address are
copied into the RGB registers, and the address register is incremented to the next cursor color location. The
MPU performs three successive read cycles (8 bits for each color) using RS0 – RS4 to select the cursor
color registers. Following the blue read cycle, the contents of the cursor color location at the address
specified by the address register are copied into the RGB registers, and the address register again
increments. A block of color values in consecutive locations can be read by writing the start address and
performing continuous RGB read cycles until the entire block has been read.
Reading Cursor Color Data
2.4.3
The 64 x 64 x 2 cursor RAM is accessed in a planar format. The TVP3025 does not support a 32 x 32 cursor.
Therefore, bit CR32 in command register 3 is nonfunctional and reading/writing to this bit performs no
operation. Bits CR30 and CR31 in command register 3 become the load inputs to the 2 MSBs of a 10-bit
address counter, therefore, these bits must be written in command register 3 before the lower 8 bits are
written to the address counter through the MPU port. In the planar format, only 9 address bits are used. The
tenth bit is to determine which plane (0 or 1) data of the cursor RAM array is accessed. A single address
presented to the cursor RAM accesses eight bit locations in plane 0 or 1, depending on the state of address
bit 9.
Accessing the Cursor RAM
After each access in the planar format, the address increments. The MPU uses a 10-bit address counter
to access the cursor array RAM array. Any write to the address counter after cursor auto-incrementing has
been initiated resets the cursor auto-incrementing logic until the cursor RAM array has again been
accessed. Cursor auto-incrementing will then begin from the address written. A read from the address
counter does not reset the cursor auto-incrementing logic. The color palette RAM and cursor RAM share
the same external address register, and MPU addressing for this and all other registers is determined by
the external RS0–RS4 select terminals (see Table 2–2).
2.4.4
The command bit CR01 is used to specify whether the MPU is reading and writing 8- or 6-bits of color
information each cycle. For 8-bit operation, D0 is the LSB and D7 is the MSB of color data. For 6-bit
operation, color data is contained on the lower 6 bits of the data bus, with D0 the LSB and D5 the MSB of
6-Bit/8-Bit Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3025-175 | Video Interface PALETTE(三PLL，視頻接口調(diào)色器) |
| TVP3030-175 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-220 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3025-135PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-175PCE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220MDN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3025-220PCE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| TVP3026 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
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