參數(shù)資料
型號(hào)： TVP3030-220
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁(yè)數(shù)： 14/107頁(yè)
文件大?。?/td> 689K
代理商： TVP3030-220
1–8
1.5
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
160
RCLK
O
Reference clock output. RCLK can be programmed to output either the pixel clock
PLL (power up default) or the loop clock PLL. The pixel clock PLL is selected to
provide a reference clock to the VGA controller. In this configuration, the VGA
controller returns VGA data and video controls along with a synchronous clock
which becomes the TVP3030 dot clock source via CLK0. For all other modes, the
loop clock PLL is selected to provide the reference clock. In this configuration, the
pixel clock PLL (or external clock) becomes the TVP3030 dot clock source. The
reference clock is used to generate VRAM shift clocks (or clock a VGA controller)
and generate video controls. The pixel port (or VGA port) and video controls are
latched by LCLK. The loop clock PLL controls the phase of RCLK to phase-lock
the received LCLK with the internal dot clock.
For systems that use SCLK as the VRAM shift clock, RCLK should be connected
to LCLK. An external buffer may be used between RCLK and LCLK if SCLK is also
buffered, within the timing constraints of the TVP3030. RCLK is not gated off
during blank.
REF
102
I/O
Voltage reference for DACs. An internal voltage reference of nominally 1.235 V
is provided, which requires an external 0.1-
μ
F ceramic capacitor between REF
and analog GND. However, the internal reference voltage can be overdriven by
an externally supplied reference voltage.
RESET
85
I
Master reset. All the registers assume their default state after reset. The default
state is VGA mode 2 (CLK0 latching of VGA data and video controls).
RD
66
I
Read strobe input. A logic 0 on this terminal initiates a read from the register map.
Read transfer data is enabled onto the D(7–0) bus when RD is low.
RS3–RS0
64, 77–79
I
Register select inputs. These terminals specify the location in the direct register
map that is to be accessed as shown in Table 2–1.
SCLK
161
O
Shift clock output. SCLK is a gated version of the loop clock PLL output and is
gated off during blank. SCLK may be used to drive the VRAM shift clock directly.
This is intended for designs in which the graphics controller does not supply the
VRAM shift clock.
SENSE
86
O
Test mode DAC comparator output signal. This terminal is low if one or more of
the DAC output analog levels is above the internal comparator reference of
350 mV
±
50 mV.
Split shift register transfer flag. A high pulse on this terminal during blank is passed
directly to the SCLK terminal. This operation is available to meet the special serial
clocking requirements of some VRAM devices. If SFLAG is not used, SFLAG
should be connected to GND.
SFLAG
127
I
SYSBL
123
I
System blank input. SYSBL is active low. This should be selected for all modes
other than VGA mode 2. This signal is pipeline delayed before being passed to
the DACs.
相關(guān)PDF資料
PDF描述
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703-135 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TVP3030-230PPA 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3030-250MEP 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3033 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3033-175 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3033-175PPA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
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