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參數(shù)資料
| 型號： | TVP3030-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 27/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-220 |
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2–11
Loop Clock
PLL
D Q
D Q
LCLK
Dot
Clock
Input Data Latch Structure
TVP3030
RCLK
CLK0
LCLK
P(127–0)
Graphics
Accelerator
VRAM
From Pixel Clock PLL
Figure 2–2. Loop Clock PLL Operation
The bit assignments of the N-, M-, and P-value and the status register for the loop clock PLL are shown in
Table 2–13. The bits shown as logic 0 or logic 1 must be written with these fixed values. PLLEN resets the
PLL when logic 0 and enables the PLL to oscillate when logic 1. The LOCK status bit indicates that the PLL
has locked to the selected frequency when logic 1. The remaining status register bits are for test purposes.
The N-, M-, and P-value registers may be programmed to any value within the following limits.
1
1
0
N(5–0)
M(5–0)
P(1,0)
62
62
3
LESEN enables the LCLK edge synchronizer function and should be logic 1 whenever a packed-24 mode
is used. In the packed-24 modes, only one LCLK rising edge per pixel group is aligned with the internal dot
clock. For example, in 8:3 packed-24 mode, only one of the three LCLKs is aligned to the internal dot clock.
The LCLK edge synchronizer function allows selection of which LCLK edge in the sequence of pixel bus
words is aligned with the internal dot clock. For each packed-24 mode there is an optimum setting for the
LCLK edge synchonizer delay LES1 and LES0. See Table 2–14 and Section 2.8.6 for more details.
Table 2–13. Loop Clock PLL Registers
REGISTER
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
N value
1
1
N5
N4
N3
N2
N1
N0
M value
LES1
LES0
M5
M4
M3
M2
M1
M0
P value
PLLEN
1
1
1
LESEN
0
P1
P0
Status
X
LOCK
X
X
X
X
X
X
2.5.3.1
Programming for All Modes Except Packed-24
For all modes except packed-24, programming of the loop clock PLL registers depends on the system
configuration, pixel rate, color depth and pixel bus width. In addition, the internal VCO must be within its
operating range of 110 – 220 MHz for the required RCLK output frequency. To determine the proper M, N,
P, and Q register values one should know the following.
Dot clock frequency (MHz) (F
D
) – pixel rate
Bits/pixel (B) – bits/pixel including overlay fields
Pixel bus width (W) – total pixel bus width used for this mode
External division factor (K) – external frequency division between RCLK output and LCLK input
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