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參數資料
| 型號： | TVP3030-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調色器) |
| 中文描述： | 視頻接口調色板Exract（1600 × 1200,24位真彩色視頻接口調色器） |
| 文件頁數： | 38/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-220 |
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2–22
PLL-synthesized, a 50% duty cycle RCLK is generated. As compared to other packed-pixel palette DACs,
which generate the RCLK waveform using a digital state machine, the TVP3030 provides a longer RCLK
period for a given dot clock frequency. This means a higher screen refresh rate is possible using VRAM of
the same speed grade. For example, for 8:3 packed-24 mode, the RCLK PLL must be set to output a clock
that is 3/8 the frequency of the pixel clock. For a 1280 x 1024 display at 135 MHz pixel rate, a 50.6 MHz
VRAM serial clock rate can be used. See Section 2.5.3 for a description of the loop clock PLL.
Packed-24 operation using the SCLK timing mode must limit the RCLK-to-LCLK loop delay to the specified
maximum delay. The following constraints apply to packed-24 modes:
The number of LCLKs (pixel bus loads) during the active portion of the horizontal line must be
a multiple of the number of LCLKs per pixel group, i.e., a multiple of 3 for 8:3 packed-24 mode.
The number of LCLKs during the total horizontal line (active + blanked) must be a multiple of the
number of LCLKs per pixel group.
The first active pixel bus load (LCLK rising edge) of the horizontal line must load the first word
of the M-word sequence comprising the pixel group. For designs not using SCLK
(TCR5 = logic 0), the first active pixel bus load coincides with the first time SYSBL is sampled
high. For designs using SCLK (TCR5 = logic 1), the first active pixel bus load occurs two LCLKs
after the first time SYSBL is sampled high. See Figures 2–5 and 2–6.
Synchronization of the packed-24 operation is performed by the loop clock PLL. Consider an N:M packed-24
mode which packs N pixels into M pixel bus words. Internally, the TVP3030 must run through a sequence
of N dot clocks for each pixel group. The loop clock PLL supplies a clock (RCLK) which is M/N times the
dot clock frequency. The graphics accelerator uses RCLK to generate SYSBL. Initially, SYSBL could change
on any of the M LCLKs of the sequence. Once SYSBL is sampled, the TVP3030 declares the proper LCLK
as the first in the M-word sequence. However, the relationship between LCLK and the internal dot clock has
not been established. Only one LCLK rising edge in the M-word pixel group is aligned with the internal dot
clock, but which one of the M LCLKs is aligned has not been specified. This selection is important for
operation of the unpacking logic and is programmable via the LCLK edge synchronizer delay. The LCLK
edge synchronizer function allows selection of which LCLK edge of the pixel group is aligned with the internal
dot clock. For each packed-24 mode, there is an optimum setting for LES1 and LES0 (see Table 2–14).
The following steps outline a typical setup procedure for packed-24 modes:
1.
Program the pixel clock PLL for the desired dot clock frequency and poll status until locked.
2.
Select pixel clock PLL as clock source in clock selection register.
3.
Program true-color control register and multiplex control register per Table 2–16.
4.
Download palette RAM if gamma correction is being used (true-color mode).
5.
Program latch control register.
6.
Set palette bypass bit (MSC5) and color-key control register appropriately. For true-color mode,
select the palette RAM. This is the power-up default. For direct-color mode, select palette bypass.
From defaults, this can be done by setting bit MSC5 = logic 1 in the miscellaneous control register.
7.
Select loop clock PLL for output on RCLK terminal by setting MCLK/loop clock control register
bit MKC5 to logic 1.
8.
Program the loop clock PLL as described in Section 2.5.3.2 and poll status until locked.
相關PDF資料 |
PDF描述 |
|---|---|
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調色器) |
| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調色器真彩色CMOS) |
| TVP3409-135 | Advanced Video Interface PALETTE(雙PLL，視頻接口調色器真彩色CMOS) |
| TVP3703-170 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調色器) |
| TVP3703-135 | Video Interface PALETTE Exract(雙PLL，先進的視頻接口調色器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TVP3030-230PPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175PPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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