參數(shù)資料
型號(hào)： TVP3030-220
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁(yè)數(shù)： 24/107頁(yè)
文件大?。?/td> 689K
代理商： TVP3030-220
2–8
2.5.1.1
The pixel clock PLL frequency may be selected using the PLL select inputs PLLSEL(1,0) as shown in
Table 2–10. The first two selections are fixed frequency settings for standard VGA operation. Use of a
standard 14.31818 MHz crystal is assumed. When PLLSEL1 is logic 1, the frequency specified by the pixel
clock PLL N-, M-, and P-value registers is selected.
Pixel Clock PLL Frequency Selection
The frequency select inputs also apply to the loop clock PLL. When a fixed frequency is selected
(PLLSEL(1,0) = 0x), the loop clock PLL output frequency is the same as the internal dot clock frequency.
For VGA Mode 1, the pixel clock PLL should be selected as the dot clock source (CSR = 0x05) and the RCLK
terminal should pass the loop clock PLL output (MCK5 = 1). Then, when PLLSEL(1,0) changes between
a programmed frequency and a fixed frequency, the loop clock PLL does not require reprogramming.
For VGA Mode 2, CLK0 should be selected as the dot clock source (CSR = 0x07) and the RCLK terminal
should pass the pixel clock PLL output (MCK5 = 0). In this case, the loop clock PLL should be disabled (bit
P7 = 0) since its output is not used. When PLLSEL1 is logic 1, the frequency specified by the loop clock PLL
N-, M-, and P-value registers is selected.
Table 2–10. Pixel Clock PLL Frequency Selection
PLLSEL1
PLLSEL0
PIXEL CLOCK PLL FREQUENCY
LOOP CLOCK PLL FREQUENCY
0
0
25.057 MHz
25.057 MHz
0
1
28.636 MHz
28.636 MHz
1
X
Programmed by pixel clock PLL registers
Programmed by loop clock PLL registers
2.5.2
The memory clock (MCLK) PLL may be used at frequencies up to 100 MHz. Appendix A provides optimal
register values for all frequencies that can be synthesized using the common 14.31818 MHz reference. The
MCLK PLL maximum output frequency of 100 MHz may not be exceeded. The equations for the VCO
frequency and for the PLL output frequency are the same as for the pixel clock PLL.
65
M
65
N
Memory Clock PLL
Provided:
FVCO
8
FREF
Minimum VCO Frequency
FVCO
Maximum VCO Frequency
Then the PLL output frequency is :
FPLL
FVCO
2P
The N-, M-, and P-value registers may be programmed to any value within the following limits:
40
1
0
N(5–0)
M(5–0)
P(1,0)
62
62
3
If several N, M, and P selections meet the above criteria, choose the selection with the largest N(5–0).
The bit assignments of the N-, M-, and P-value and the status register for the MCLK PLL are given in
Table 2–11. The bits shown as logic 0 or logic 1 must be written with these fixed values. PLLEN resets the
PLL when logic 0 and enables the PLL to oscillate when logic 1. The LOCK status bit indicates that the PLL
has locked to the selected frequency when logic 1. The remaining status register bits are for test purposes.
The MCLK PLL and loop clock PLL are further controlled by the MCLK/loop clock control register shown
in Table 2–12.
相關(guān)PDF資料
PDF描述
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
TVP3703-135 Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TVP3030-250MEP 制造商:Rochester Electronics LLC 功能描述:- Bulk
TVP3033 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3033-175 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette
TVP3033-175PPA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
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