![](http://datasheet.mmic.net.cn/390000/TVP3030-175_datasheet_16839167/TVP3030-175_57.png)
2–41
the 24 different DAC data inputs. Value 0 corresponds to DAC data red 0 (LSB), value 7 to red 7 (MSB), value
8 to green 0 (LSB), value 15 to green 7 (MSB), value 16 to blue 0 (LSB), and value 23 to blue 7 (MSB). The
16-bit remainder that is calculated on the individual DAC data line can be read from the CRC remainder LSB
and CRC remainder MSB registers. See Sections 2.16.9 and 2.16.10 for the CRC register bit definitions.
As long as the display pattern for each screen remains fixed, the CRC result should remain constant. If the
CRC result changes, an error condition should be assumed. The CRC is calculated using the algorithm
depicted by the circuit in Figure 2–11. The user can calculate and store the CRC remainder for a test screen
in software and compare this to the TVP3030 calculated CRC remainder to verify data integrity.
LSB
D Q
0
D Q
1
D Q
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
D Q
13
D Q
14
DQ
15
DATAIN
Q15
MSB
Figure 2–11. CRC Algorithm
2.13.2
Sense Comparator Output and Test Register
The TVP3030 provides a SENSE output to support system diagnostics. SENSE can be used to determine
the presence of the CRT monitor or verify that the RGB termination is correct. SENSE is a logic 0 if one or
more of the DAC outputs exceeds the internal comparator voltage of 350 mV. The internal 350-mV reference
has a tolerance of
±
50 mV when using an external 1.235-V reference. If the internal voltage reference is
used, the tolerance is higher.
The sense comparators are also integrated with the sense test register (index: 0x3A) so that the comparison
results for the red, green, and blue comparators can be read independently through the 8-bit microinterface.
When the sense test register (STR) is read, the results are indicated in the bit positions as shown below.
INDEX: 0x3A, ACCESS: R/W, DEFAULT: UNINITIALIZED
STR BITS
D7
D6
D5
D4
D3
D2
D1
D0
Data
DIS
0
0
0
0
R
G
B
where: R = logic 1 if IOR > 350 mV
G = logic 1 if IOG > 350 mV
B = logic 1 if IOB > 350 mV
D6 – D3 are reserved
D7 is disable (logic 1) bit
NOTE:
D7 can be set to a logic 1 to disable the sense comparison function. At reset, the
sense comparison is enabled (D7 = logic 0). D6–D3 are reserved. When this
register is written to, to disable the sense comparator function, bits D6–D0 need
to be set to a logic 0.
Both the SENSE output and the sense test register are latched by the falling edge
of the internally sampled blank signal (SYSBL or VGABL depending on bit MCR6).
In order to have stable voltage inputs to the comparators, the frame-buffer inputs
should be set such that data entering the DACs remains unchanged for a sufficient
period of time prior to and after the BLANK-signal falling edge.