![](http://datasheet.mmic.net.cn/390000/TVP3030-175_datasheet_16839167/TVP3030-175_54.png)
2–38
2.9.4
The cursor supports an interlaced display when bit CCR5 in the cursor control register is logic 1. For the
purposes of this discussion assume that the interlaced display consists of an even field of scan lines
numbered 0, 2, 4, . . ., etc., and an odd field of scan lines numbered 1, 3, 5, . . ., etc. Scan line 0 is the first
scan line at the top of the display. When interlaced mode is enabled and cursor position y (CPy) is greater
than 64 (0x40) and less than or equal to 4095 (0xFFF), the first cursor line displayed depends on the state
of the ODD/EVEN terminal and value of CPy.
Interlaced Cursor Operation
If CPy is an even number, the data in row 0 of the cursor RAM array will be displayed during the even field
(ODD/EVEN = logic 0), followed by rows 2, 4, . . ., 62 on successive scan lines. The data in row 1 of the cursor
RAM array will be displayed during the odd field (ODD/EVEN = logic 1), followed by rows 3, 5, . . ., 63 on
successive scan lines.
If CPy is an odd number, the data in row 0 of the cursor RAM array will be displayed during the odd field
(ODD/EVEN = logic 1), followed by rows 2, 4, . . ., 62 on successive scan lines. The data in row 1 of the cursor
RAM array will be displayed during the even field (ODD/EVEN = logic 0), followed by rows 3, 5, . . ., 63 on
successive scan lines.
If CPy is between 0 and 64 (0x40), the cursor is partially off the top of the screen. In this case, the data in
the first displayed row of the cursor RAM (row N) is always displayed on scan line 0, which is the first scan
line of the even field, followed by cursor rows N + 2, N + 4, . . ., etc. on successive scan lines. The data in
cursor row N + 1 is displayed on scan line 1, which is first scan line of the odd field, followed by cursor rows
N +3, N + 5, . . ., etc. on successive scan lines.
The CCR6 bit of the cursor control register allows the polarity of the received ODD/EVEN signal to be
inverted when the CCR6 bit is set to logic 1.
2.10 Color-Key Switching
The TVP3030 provides an integrated mechanism for switching between direct-color images and overlay
graphics or between direct-color images and true-color (gamma corrected) images midscreen. The
color-key switching function combines images on screen based on color comparison with stored color range
registers.
The color-key switching function is controlled by the color-key-control register (index: 0x38, see Section
2.16.7 for register definition). For switching between direct-color and true-color, a true-color mode must be
selected from Table 2–16. The incoming red, green, and blue color fields are compared with their respective
color range registers (before gamma correction). The overlay terminals could also be used for the color
comparison, although the overlay information is not displayable in true-color mode. For switching between
direct-color and overlay, a direct color mode must be selected from Table 2–16 and the VGA port must be
disabled (MCR7 = logic 0). In all cases, the palette bypass bit (MSC5) should be logic 1. The color-key
control register is then used to enable/disable the red, green, blue, and/or overlay range comparators and
to define the polarity of the color-key switching function. The comparison values are then written to the eight
8-bit color key range registers; color key overlay (low, high), color key red (low, high), color key green (low,
high), and color key blue (low, high). These registers are accessed through index 0x30 through index 0x37.
The granularity for color-key switching is on a pixel-by-pixel basis.