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參數(shù)資料
| 型號： | TVP3030-220 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| 中文描述： | 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器） |
| 文件頁數(shù)： | 51/107頁 |
| 文件大?。?/td> | 689K |
| 代理商： | TVP3030-220 |
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2–35
2.9
The TVP3030 has an on-chip three-color 64x64 pixel user-definable cursor. The cursor operation defaults
to the XGA standard, but X-windows and three-color modes are also available (see Section 2.9.3). The
cursor operates in both noninterlaced and interlaced applications.
On-Chip Cursor
The pattern for the 64 x 64 cursor is provided by the cursor RAM, which may be accessed by the MPU at
any time. Cursor positioning is performed via the cursor-position (x,y) registers (see register bit definitions
in Section 2.16.5). Positions x and y are defined in the TVP3030 increasing from left to right and from top
to bottom, respectively, as seen on the display screen.
On-chip cursor control is performed by the indirect cursor-control register (index: 0x06). The direct cursor
control register provides an alternate means of enabling and disabling the cursor and selecting the cursor
mode. See the cursor-control register bit definitions in Section 2.16.3.
2.9.1
Cursor RAM
The 64 x 64 x 2 cursor RAM is used to define the pixel pattern within the 64x64 pixel cursor window. It is
not initialized and may be written to or read by the MPU at any time, even when the cursor is enabled.
The cursor RAM address zero is at the top left corner of the RAM as shown in Figure 2–8. The cursor plane
0 bits for the entire cursor array are stored in the first 512 bytes of the RAM and the cursor plane 1 bits for
the entire cursor array are stored in the last 512 bytes of the RAM. Information for eight cursor pixels is stored
in each byte. The MSB (D7) corresponds with the first or leftmost pixel displayed on the screen.
The 64 x 64 x 2 cursor RAM stores a total of 8192 bits and is accessed through the 8-bit MPU data bus. There
are therefore 1024 bytes stored in the RAM and a 10-bit address is used. The upper two bits of the cursor
RAM address (A9, A8) are written to cursor control register (index: 0x06) bits CCR3 and CCR2. The MSB
of the address (CCR3) selects cursor plane 0 or cursor plane 1. The lower eight bits of the cursor RAM
address (A7–A0) are written to the cursor RAM write address register (direct register: 0000) for writing to
the RAM and to the cursor RAM read address register (direct register: 0011) for reading the RAM. Then the
plane 0 or 1 data for the first eight pixels is written to the cursor RAM data register (direct register: 1011).
This stores the cursor pixel data in the cursor RAM and automatically increments the cursor RAM address
register. The upper two bits of the cursor RAM address also increment when the lower eight bits roll over
from 0xFF to 0x00. A second write to the cursor RAM data register loads the plane 0 or 1 data for the next
eight cursor pixels, and so on. Update of the entire cursor RAM requires 1024 writes to the cursor RAM data
register.
To read from the cursor RAM, the address of the first cursor-RAM location to be read is loaded using CCR3
and CCR2 and the cursor-RAM read address register. Then a read is performed on the cursor-RAM data
register (direct register: 1011) which reads the plane 0 or 1 data for eight consecutive pixels. Similar to the
cursor RAM write operation, when the read is completed, CCR3 and CCR2 and the cursor-RAM address
register are automatically incremented and further reads read successive cursor RAM locations. Upload of
the entire cursor RAM requires 1024 reads of the cursor RAM data register.
NOTES:
The cursor RAM upper address bits CCR3 and CCR2 in the cursor control register
default to zeros after reset. Since software normally sets these bits to zeroes before
accessing the cursor RAM, it may not be necessary to write to CCR3 and CCR2.
Internally, the entire 10-bit address is loaded into the address counter after a write
to the cursor RAM address register (direct register, 0000 or 0011), so CCR3 and
CCR2 should be written first, if they are to be changed.
Vertical retrace is determined by detecting 2048 or 4096 pixel clocks between rising
edges of the internal BLANK signal. CCR4 selects 2048 when logic 0 and 4096
when logic 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TVP3030-250 | Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器) |
| TVP3409-170 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| TVP3409-135 | Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS) |
| TVP3703-170 | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
| TVP3703-135 | Video Interface PALETTE Exract(雙PLL，先進(jìn)的視頻接口調(diào)色器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TVP3030-230PPA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3030-250MEP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TVP3033 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Video Interface Palette |
| TVP3033-175PPA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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