參數(shù)資料
型號(hào): TVP3030-220
廠商: Texas Instruments, Inc.
英文描述: Video Interface PALETTE Exract(1600×1200,24位真彩色視頻接口調(diào)色器)
中文描述: 視頻接口調(diào)色板Exract(1600 × 1200,24位真彩色視頻接口調(diào)色器)
文件頁數(shù): 19/107頁
文件大?。?/td> 689K
代理商: TVP3030-220
2–3
Table 2–2. Indirect Register Map (Extended Registers) (Continued)
INDEX
R/W
DEFAULT
REGISTER ADDRESSED
BY INDEX REGISTER
0x3D
R
XX
CRC Remainder MSB
0x3E
W
XX
CRC Bit Select
0x3F
R
0x30
Device ID
0xFF
W
XX
Software Reset
2.2
The color palette RAM is addressed by an internal 8-bit address register for reading/writing data from/to the
RAM. This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to the internal clocks but are performed within one dot clock. Therefore, read/write
accesses do not cause any noticeable disturbance on the display.
Color Palette RAM
The color palette RAM is 24 bits wide for each location and 8 bits wide for each color. Since a MPU access
is eight bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen. If
the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.
However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with the INMOS
IMSG176 and Brooktree Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and
fills the two LSBs with 0s after the color palette. The multiplexer then feeds the data to the DAC. The test
mode data register and the CRC calculation both take data after the output multiplexer, enabling total system
verification. The color palette access is described in the following two sections, and it is fully compatible with
IMSG176/8 and Bt476/8.
2.2.1
Writing to Color-Palette RAM
To load the color palette, the MPU must first write to the palette RAM write address register (direct register:
0000) with the address where the modification is to start. The selected palette RAM location is loaded a byte
at a time by writing a sequence of three bytes (red, green, and blue) to the palette RAM data register (direct
register: 0001). After the blue write cycle, the palette RAM address register increments to the next location,
which the MPU may modify by simply writing another sequence of red, green, and blue data.
2.2.2
Reading From Color-Palette RAM
Reading from the palette is performed by writing to the palette read address register (direct register: 0011)
with the location to be read. Three successive MPU reads from the palette RAM data register produce red,
green, and blue color data (6 or 8 bits depending on the 8/6 mode) for the specified location. Following the
blue read cycle, the address register is incremented. Since the color-palette RAM is dual ported, the RAM
may be read during active display without disturbing the video.
2.2.3
8- or 6-Bit Mode Selection
The 8-bit or 6-bit DAC resolution is software selectable. The default is 6-bit resolution. Bit MSC3 in the
miscellaneous control register selects 8-bit operation (logic 1) or 6-bit operation (logic 0).
2.2.4
Pixel Read-Mask Register
The pixel read-mask register (direct register: 0010) is an 8-bit register used to enable or disable a bit plane
from addressing the color-palette RAM in the pseudo-color and VGA modes. Each palette address bit is
logically ANDed with the corresponding bit from the read-mask register before going to the palette-page
register and addressing the palette RAM.
2.2.5
Palette-Page Register
The palette-page register (index: 0x1C) allows selection of multiple color look-up tables stored in the palette
RAM when using a mode that addresses the palette RAM with less than 8 bits. When using 1, 2, or 4 bit
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