參數(shù)資料
型號： TVP3030-220
廠商： Texas Instruments, Inc.
英文描述： Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
中文描述： 視頻接口調(diào)色板Exract（1600 × 1200,24位真彩色視頻接口調(diào)色器）
文件頁數(shù)： 29/107頁
文件大小： 689K
代理商： TVP3030-220
2–13
Table 2–14. Loop Clock PLL Settings for Packed-24 Modes
PACKED-24 MODE
BIT TCR5 (Index 0x18)
N-VALUE REGISTER
M-VALUE REGISTER
4:3
0
0xFD
0xBE
8:3
0
0xF9
0xBE
16:3
0
0xF1
0xBE
5:4
0
0xFC
0xBD
5:2
0
0xFC
0xBF
5:1
0
0xF7
0xBF
4:3
1
0xFD
0xBE
8:3
1
0xF9
0xBE
16:3
1
0xF1
0xBE
5:4
1
0xFC
0xBD
5:2
1
0xFC
0xBF
5:1
1
0xF7
0xBF
The P and Q frequency dividers must be programmed so that the VCO is within its operating range. The
VCO frequency is post scaled by the P-divider followed by the Q-divider. The P-divider register (P) can take
on values of 0, 1, 2, or 3 which correspond to division factors of 1, 2, 4, or 8. The Q-divider register (Q) is
stored in bits 2 – 0 of the MCLK/loop clock control register (index: 0x39) and can take on values of 0, 1, 2,
. . ., 7 which correspond to division factors of 2, 4, 6, . . ., 16. The total post-scalar frequency division factor
is:
F
VCO
F
D
Next, set F
VCO
to the lower limit of 110 MHz and solve for Z:
Z
F
D
Finally, determine the P and Q values:
IF Z
16 then P
largest integer less than log
2
(Z), Q
IF Z
16 then P
3, Q
Z
2
P
1
(Q
1)
K
65
65
N
M
110
K
65
65
N
M
0
smallest integer greater thanZ
16
16
Set bits 7–2 of the P-value register to 1111 10. This enables the PLL to oscillate and enables the LCLK edge
synchronizer function. To reset the PLL, set bit 7 of the P-value register to logic 0.
2.5.3.3
Typical Device Connection
After reset, the TVP3030 defaults to VGA mode 2 (VGA pass through mode, see Section 2.8.2). The RCLK
terminal outputs the pixel clock PLL frequency which is selected by PLLSEL1 and PLLSEL0. CLK0 is
selected as the clock source and the VGA port is selected as well as VGABL, VGAHS, and VGAVS and
these are latched with CLK0. The MCLK PLL outputs the default 50.11 MHz clock frequency.
Figure 2–3 shows the typical device connection for a system with VRAM clocked by the graphics
accelerator. After power up, the pixel clock PLL is output on RCLK and this clock drives the graphics
accelerator’s VGA controller and video timing logic. The accelerator’s output clock is output synchronous
to the VGA data and is input to the TVP3030 CLK0 input as the dot clock source.
Figure 2–4 shows the typical device connection for a system with VRAM clocked by the TVP3030. In this
case, the RCLK is tied back to the LCLK and this same clock drives the graphics accelerator’s VGA
controller and video timing logic. If necessary, the RCLK and SCLK signals may be externally buffered within
the timing constraints (RCLK to LCLK delay) of the TVP3030. The pixel clock PLL is output on RCLK after
power up.
相關(guān)PDF資料
PDF描述
TVP3030-250 Video Interface PALETTE Exract(1600×1200，24位真彩色視頻接口調(diào)色器)
TVP3409-170 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3409-135 Advanced Video Interface PALETTE(雙PLL，視頻接口調(diào)色器真彩色CMOS)
TVP3703-170 Video Interface PALETTE Exract(雙PLL，先進的視頻接口調(diào)色器)
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