參數(shù)資料
型號(hào): V30MZ
英文描述: V30MZ(TM) Hardware (Preliminary) | User's Manual[01/2002]
中文描述: V30MZ(TM)硬件(初步)|用戶手冊[01/2002]
文件頁數(shù): 13/89頁
文件大小: 418K
代理商: V30MZ
13
CHAPTER 1 GENERAL DESCRIPTION
The V30MZ is a CPU core that is an improved version of the V30MX, which itself enhances the bus efficiency of
the
μ
PD70116H (other name: V30HL), an original NEC microprocessor.
The V30MZ raises the bus efficiency by realizing 1 clock/bus cycle. The incorporation of an internal pipeline
considerably raises the instruction execution time, enabling fast processing comparable to that of RISC
microprocessors.
Compared to the V30MX's 4.3 MIPS (33-MHz operation, no wait), the V30MZ realizes a processing performance
of 35 MIPS (66-MHz operation, no wait).
1.1 Features
(1)
(2)
(3)
(4)
Processing performance: 35 MIPS (66-MHz operation, no wait)
CMOS static design (internal system clock can be fully stopped)
1 bus cycle: 1 clock
External bus interface
Address bus: 20 bits
Data bus: 16 bits (separate input/output buses)
Bus hold function
Standby function (HALT mode)
(5)
(6)
1.2 Symbol Diagram
UBEB
HLDAK
BS (3:0)
DO (15:0)
DI (15:0)
DBINT
A (19:0)
out
out
out
out
out
out
out
out
out
NMI
POLLB
READYB
HLDRQ
INT
CLK
RESET
TBO
(42:0)
TBI
(22:0)
TEST
BUNRI
in
in
in
out
BUSLOCKB
DBMODE
DBA20
out
out
out
in
in
in
in
in
in
in
in
in
in
DBNMIM
DBRD
DBWR
DBHLTST
TILEN (3:0)
TBRA
TINTA
TEOI
out
out
out
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