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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 47/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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47
CHAPTER 4 BUS CONTROL FUNCTIONS
The V30MZ executes 1 bus cycle in 1 clock.
Since accessing memory integrated on the same chip is possible in just 1 clock, it is possible to configure systems
that take advantage of both small-capacity, high-speed on-chip memory and large-capacity, low-cost external
memory by combining a wait insertion function.
4.1 Interface between V30MZ and Memory
As the V30MZ uses a 16-bit data bus, it is capable of transferring 16-bit word data in 1 bus cycle. However, this
applies only when an address generated by an instruction is even (A0 = 0), and if it is odd (A0 = 1) a word data
transfer requires 2 bus cycles.
Figure 4-1 shows the interface between the V30MZ and memory.
Figure 4-1. Interface between V30MZ and Memory
A19 to A1
V30MZ
A0
UBEB
DI15 to DI0
DO15 to DO0
Memory
Upper bank
(512 K bytes)
CSB
Memory
Lower bank
(512 K bytes)
DI15
to DI8
Address bus (19)
DO15
to DO8
DI7
to DI0
DO7
to DO0
8
8
8
8
Data input bus (16)
Data output bus (16)
CSB
In Figure 4-1, A0, when active low, enables the lower bank byte data of memory. Furthermore, aside from the
information from the address bus, the UBEB signal is output and when active low this also enables the byte data of
the memory higher bank.
(1) When accessing word data at odd address
In the first bus cycle, UBEB = 0 and A0 = 1, and only the higher byte is accessed and then UBEB = 1 is
automatically set, the lower 16 bits (A15 to A0) of the address information is incremented (+1). That is, A0 = 0 is
set, and the lower byte at the next address is accessed.
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