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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 73/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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73
APPENDIX A LIST OF INSTRUCTION EXECUTION CLOCK COUNTS
This appendix shows the number of execution clocks for each instruction under conditions (1) to (7) listed below.
For details on the functions of each instruction, refer to the
16-Bit V Series Instruction User’s Manual
.
(1)
(2)
(3)
(4)
(5)
Instruction decoding is completed.
No wait state occurs during memory access or I/O access.
There is no bus hold request.
Word data is allocated to even addresses.
Registers required for calculating effective addresses (BW, BP, SP, IX, IY, etc.) do not change at
immediately preceding instruction.
There is only 1 register required for calculating effective addresses.
The branching destination of a branch instruction is an even address.
Note 1
Note 2
Note 3
(6)
(7)
Note 4
Note 5
Notes 1.
If a wait state is generated, add the number of clocks of the wait state to the number of instruction
execution clocks.
2.
When access to word data allocated to odd addresses is performed, add 1 clock.
3.
When using a register that changed in the immediately preceding instruction for calculating the
effective address, add 1 clock.
(However, 1 clock does not increase in the case of the LDEA instruction and the repeat prefetch
instruction.)
Moreover, in the case of consecutive PUSH or POP instruction, the number of execution clocks does
not increase (they are all executed in 1 clock.)
4.
If there are two registers required for calculating the effective address (for example MOV AW,[BW+IX]),
add 1 clock.
5.
If branching to an odd address is performed, add 1 clock.
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