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參數(shù)資料
| 型號(hào)： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊(cè)[01/2002] |
| 文件頁(yè)數(shù)： | 65/89頁(yè) |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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65
CHAPTER 6 STANDBY FUNCTIONS
6.1 Setting of Standby Mode
Executing a HALT instruction sets the standby (HALT) mode.
In the standby mode, the clock is supplied only to the circuit related to the function required for releasing the
standby mode and the circuit related to the bus hold function, and its supply to all other circuits is stopped.
As a result, the system's power consumption is considerably reduced.
6.2 Standby Mode
When the V30MZ enters the standby mode, the BS3 to BS0 signals output the HALT status for 1 clock. Then the
A19 to A0 signals, the UBEB signal, and the BS3 to BS0 signals become high level. DO15 to DO0 outputs become
undefined.
Figure 6-1. Timing to Enter Standby Mode
The bus hold function is also valid in the standby mode, but when the bus hold acknowledge period ends, the
system returns to the standby mode. However, when the system returns to the standby mode, there is no HALT
status output from the BS3 to BS0 pins (the idle status continues).
CLK (input)
A19 to A0 (output)
UBEB (output)
BS3 (output)
DO15 to DO0 (output)
Undefined
BS2 (output)
BS1 (output)
BS0 (output)
H
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