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| 型號： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊[01/2002] |
| 文件頁數(shù)： | 35/89頁 |
| 文件大?。?/td> | 418K |
| 代理商： | V30MZ |
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CHAPTER 3 CPU FUNCTIONS
35
Figure 3-6. Relationship between Segment Register, Offset Address and Physical Address
0
0
Segment register (16 bits)
0
3
1
4
2
0
19
0
0
15
Offset address (16 bits)
0
19
Physical address (20 bits)
+
As shown in Figure 3-6, the physical address is a sum of 16 times the segment register content (4 bits shifted to
left) and offset value. At this time, the segment register content and offset value are treated as unsigned data.
In a program which is created as a set of multiple segments for which allocation addresses are specified by
physical addresses, each segment is compiled and assembled individually and becomes one or a number of object
modules. Each object module has a segment name, size, content classification, control information, etc., and
becomes a parameter in execution of link processing.
Multiple object modules are linked and the segment base addresses corresponding the physical addresses are
specified and become ready to be loaded to actual memory.
3.4.2 Segment configuration
The V30MZ can distinguish 4 kinds of segment (program, stack, data 0, data 1) and define them. For each
segment the start address is specified by one of the following 4 segment registers.
The BCU uses different segment registers for generation of physical addresses depending on the type of memory
bus cycle.
Program segment register (PS)
Stack segment register (SS)
Data segment 0 register (DS0)
Data segment 1 register (DS1)
The offset address within each segment is specified by a specific register or effective address. Table 3-2 shows
correspondence between each segment register and offset addressing.
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