
85
APPENDIX B INDEX
[A]
A19 to A0................................................................. 19
AC............................................................................ 28
Addressing Mode..................................................... 42
Addressing with based index................................... 45
AH............................................................................ 25
AL............................................................................ 25
Auxiliary carry flag................................................... 28
AW........................................................................... 25
[B]
Based addressing.................................................... 45
BH............................................................................ 25
BL............................................................................ 25
BP............................................................................ 25
Break flag ................................................................ 29
BRK......................................................................... 29
BS3 to BS0.............................................................. 19
BUNRI ..................................................................... 22
BUS CONTROL FUNCTIONS................................. 47
Bus Hold Function................................................... 54
BUSLOCKB............................................................. 20
BW........................................................................... 25
[C]
Carry flag................................................................. 27
CH ........................................................................... 25
CL............................................................................ 25
CLK.......................................................................... 21
Control flag.............................................................. 26
CPU FUNCTIONS................................................... 25
CW........................................................................... 25
CY............................................................................ 27
[D]
Data address........................................................... 43
Data segment 0....................................................... 37
Data segment 1....................................................... 37
Description of Pin Statuses ..................................... 19
DH ........................................................................... 25
DI15 to DI0 .............................................................. 19
Differences between V30MZ and V30 HL, V30MX.. 14
DIR .......................................................................... 29
Direct addressing............................................... 42, 44
Direction flag............................................................29
DL ............................................................................25
DO15 to DO0 ...........................................................19
Double word data configuration ...............................32
DS0..........................................................................25
DS1..........................................................................25
DW...........................................................................25
Dynamic relocation ..................................................37
[E]
Effective Address.....................................................39
[F]
Format of object code ..............................................41
[G]
General-purpose registers .......................................25
[H]
Handling of Unused Pins .........................................23
Hardware Interrupt...................................................58
HLDAK.....................................................................21
HLDRQ.....................................................................20
[I]
IE..............................................................................29
Immediate addressing..............................................43
Indexed addressing..................................................45
Index register ...........................................................30
Initial Value of Registers after Reset........................69
Instruction address...................................................42
Instruction Prefetch..................................................33
Instruction Set..........................................................40
INT ...........................................................................21
Interface between V30MZ and I/O...........................49
Interface between V30MZ and Memory...................47
Interrupt Acknowledge Cycle ...................................59
Interrupt enable flag.................................................29
INTERRUPT FUNCTIONS.......................................55
Interrupt Servicing in Execution of Block Processing
Instruction ................................................................62
Interrupt Vector Table Configuration........................56
I/O addressing..........................................................43
I/O Map ....................................................................32
I/O space..................................................................32