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參數(shù)資料
| 型號(hào)： | V30MZ |
| 英文描述： | V30MZ(TM) Hardware (Preliminary) | User＇s Manual[01/2002] |
| 中文描述： | V30MZ（TM）硬件（初步）|用戶手冊(cè)[01/2002] |
| 文件頁(yè)數(shù)： | 50/89頁(yè) |
| 文件大小： | 418K |
| 代理商： | V30MZ |
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CHAPTER 4 BUS CONTROL FUNCTIONS
50
4.3 Read/Write Timing of Memory and I/O
The V30MZ executes one bus cycle in at least 1 clock.
4.3.1 Read timing of memory and I/O
The V30MZ outputs the addresses (A19 to A0), UBEB signal, and bus status (BS3 to BS0) in synchronization with
the rising edge of the clock (CLK).
Data (DI15 to DI0) is read at the rising edge of the next CLK signal, and the READYB signal is sampled at the
same time. If the READYB signal is low at this time, the operation goes to the next bus cycle, and if the READYB
signal is high, the operation goes to the wait cycle (TW), and the current bus cycle is extended. In the TW state, the
A19 to A0 signals and the UBEB signal maintain their output value, but the BS3 to BS0 signals become high level.
Figure 4-2. Read Timing of Memory and I/O (1/2)
(a) With No Wait
CLK (input)
A19 to A0 (output)
UBEB (output)
BS3 (output)
DI15 to DI0 (input)
READYB (input)
T
X
Don't care
Don't care
BS2 (output)
BS1 (output)
BS0 (output)
H
During memory read: H
During I/O read: L
During memory read: L
During I/O read: H
Remark
{
indicates the sampling timing.
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