參數(shù)資料
型號(hào): W6692A
英文描述: TE Mode S/T Controller with PCI 2.2 Interface and ACPT
中文描述: TE模S / T的2.2與PCI控制器接口和ACPT
文件頁數(shù): 24/101頁
文件大?。?/td> 851K
代理商: W6692A
W6692A
- 24 -
TABLE 7.3 LAYER 1 INDICATION CODES
INDICATION
SYM
CODE
DESCRIPTIONS
Clock enabled
CE
0111
Internal clocks are enabled
Deactivate request
downstream
DRD
0000
Deactivation request by S interface, i.e INFO 0
received
Level detected
LD
0100
Signal received, receiver not synchronous
Activate request
downstream
ARD
1000
INFO 2 received
Test indication
TI
1010
Analog loopback activated or continuous zeros or
single zeros transmitted
Awake test indication
ATI
1011
Level detected during test function
Activate indication with
priority class 1
AI8
1100
INFO 4 received, D channel priority is 8 or 9
Activate indication with
priority class 2
AI10
1101
INFO 4 received, D channel priority is 10 or 11
Clock disabled
CD
1111
Layer 1 deactivated, internal clocks are disabled
7.2.3.2 State Transition Diagrams
The followings are the state transition diagrams, which implement the activation/deactivation state
matrix in I.430 (TABLE 5/I.430). The "command" and "s receive" entries in each state octagon keep
the state, the "indication" and "s transmit" entries in each state octagon are the state outputs. For
example, at "F3 Deactivated with clock" state, the layer 1 will stay at this state if the command is
"ECK" and the INFO 0 is received on S interface. At this state, it provides "CE" indication to the
microprocessor and transmits INFO 0 on S interface. The "AR8/10" command causes transition to F4
and non-INFO 0 signal causes transition to F5. Note that the command code writtern by the
microprocessor in CIX register and indication code written by layer 1 in CIR register are transmitted
repeatedly until a new code is written.
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