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參數(shù)資料
| 型號(hào)： | W6692A |
| 英文描述： | TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| 中文描述： | TE模S / T的2.2與PCI控制器接口和ACPT |
| 文件頁(yè)數(shù)： | 31/101頁(yè) |
| 文件大?。?/td> | 851K |
| 代理商： | W6692A |
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W6692A
Publication Release Date: July 2000
- 31 -
Revision A1
7.2.7 Test Functions
The W6692A provides loop and test functions as follows:
- Digital loop via DLP bit in D_MODE register: In the layer 2 block, the transmitted 2B+D data are
internally looped (from HDLC transmitter to HDLC receiver), and in the PCM ports, the
transmitted B channels are internally looped (from PCM inputs to PCM outputs). The clock
timings are generated internally and are independent of the S bus timing. This loop function is
used for test of PCM and higher layer functions, excluding layer 1. After hardware reset, W6692A
will power down if S bus is not connected or if there is no signal on the S bus. In this case, the C/I
command ECK must be issued to power up the chip.
- Analog loop via the C/I command EAL: The analog S interface transmitter is internally connected
to the S interface receiver. When the receiver has synchronized itself to the internal INFO 3
signal, the message "Test Indication" or "Awake Test Indication" is delivered to the CIR register.
No signal is transmitted over the S interface.
In this mode, the S interface awake detector is enabled. Therefore if a level (INFO 2/ INFO 4) is
detected on the S interface, this will be reported by the "Awake Test Indication (ATI)" indication.
- Remote loopback via RLP bit in D_MODE register: The digital 2B data received from the S
interface receiver is loopbacked to the S interface transmitter. The D channel is not looped. When
RLP is enabled, layer 1 D channel is connected to HDLC port and DLP cannot be enabled.
- Transmission of special test signals via layer 1 command:
* Send Single Pulses (SSP): To send isolated single pulses of alternating polarity, with pulse width
of one bit time, 250 uS apart, with a repetition frequency of 2 KHz.
* Send Continuous Pulses (SCP): To send continuous pulses of alternating polarity, with pulse
width of bit time. The repetition frequency is 96 KHz.
Fig.7.7 SSP and SCP Test Signals
250 uS
(a) Single pulses
(b) Continuous pulses
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W6692ACD | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694A | TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | USB Bus ISDN S/T-Controller |
| W7020 | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
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